Planar Bulk Research Articles

Performance optimisation of junctionless FET in nano regime using segmented channel - A 3D numerical simulation study

The performance of the planar junctionless devices is improved using corrugated substrate also known as SegFET device. Bulk and SOI based planar junctionless devices are investigated for their performance enhancement using 3D numerical simulations. Four devices, (i) BPJLT - junctionless device on bulk planar substrate (ii) BPJL SegFET - junctionless device on bulk corrugated substrate (iii) SOIJLT - junctionless device on SOI planar substrate (iv) SOIJL SegFET - junctionless device on SOI corrugated substrate, are taken for study. BPJL SegFET and SOIJL SegFET devices are compared against BPJLT and SOIJLT devices to find out the benefit of the corrugated substrate in junctionless devices. The parameters ION, IOFF, ION/IOFF ratio and unity gain frequency (fT) are used for comparison. Replacing the planar substrate with corrugated substrate improves the ION/IOFF ratio but degrades fT. The impact of corrugated substrate on bulk device is more compared to SOI device. The impact of VSTI region (WVSTI) and stripe region widths (WSPACE), and permittivity of VSTI region (KVSTI) are also analyzed. While better ION/IOFF performance can be achieved by using higher permittivity in VSTI region and by increasing the VSTI width, higher fT is obtained by using higher stripe width. A full factorial DOE simulation has also been performed in order to rank the above three parameters with respect to ION, IOFF and ION/IOFF at the end. An overall ranking has also been provided which predicts WVSTI to be the most sensitive parameter irrespective of ION, IOFF or ION/IOFF.

Impact of aging on the soft error rate of 6T SRAM for planar and bulk technologies

This paper evaluates the impact of aging on the radiation sensitivity of 6T SRAM for two planar bulk technologies. This study is motivated by the growing impact of aging and radiation effects on the reliability of CMOS technology. A modelling methodology dedicated to this new phenomenon is proposed. This modelling uses the radiation modelling device MUSCA SEP3 and an electrical aging modelling. First, the impact of aging on SEE sensitivity is studied through a parametric modeling of the threshold voltages of the transistors composing the 6T SRAM. Then, an operative avionics environment is modelled in order to evaluate the consequences on reliability.

Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies

Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to address this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technologies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect.

Effects of Threshold Voltage Variations on Single-Event Upset Response of Sequential Circuits at Advanced Technology Nodes

Threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of transistors plays an important role in single-event upsets (SEU) and system power consumption. Effect of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> on single-event upsets can be very different for different technologies. SEU responses of flip-flops and logic circuits in 20-nm bulk planar and 16-nm bulk FinFET technologies with different V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> options are investigated. Results show that for the 20-nm bulk planar technology, the design with the highest threshold voltage among all V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> options shows the lowest SEU cross-section for alpha particle irradiation. For the 16-nm FinFET technology, the option with the highest threshold voltage shows the highest SEU cross-section. As frequency increases, the SEU cross-section of the highest V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> design shows a faster increase and a larger curve slope due to increased single-event transient (SET) pulse width compared to the lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> designs for the 16-nm FinFET technology node.

Analysis of Bulk FinFET Structural Effects on Single-Event Cross Sections

A set of upset criteria based on circuit characteristic switching time frame is developed and used to bridge transistor-level TCAD simulations to circuit-level single-event (SE) upset cross sections for advanced (fast and small) digital circuits. Interpretation of the measured and 3D TCAD simulated single-event upset (SEU) responses of bulk planar circuits and bulk FinFET circuits using the short-time based upset criteria quantitatively explains the observed divergence of low-LET FinFET cross sections from simple geometric scaling predictions. Comparisons of measured and computed single-event cross section responses show excellent agreement.

Study of silicon nanowire field effect transistor with different oxide material using fettoy simulator

As the MOSFET gate length enters the nanometer regime, short channel effects (SCE) such as threshold voltage (VT) roll off and drain- induced- barrier- lowering becomes increasingly significant, which limits the scaling capability of planar bulk or silicon-on-insulator (SOI) MOSFET. At the same time the relatively low carrier mobility in silicon may also degrade the MOSFET device performance. For these reasons, various novel device structures and materials such as silicon nanowire transistors, carbon nanotubes, new channel materials, molecular transistors are being extensively explored. Among all these, promising post CMOS structures, the silicon nanowire transistor (SNWT) has its unique advantage - The SNWT is based on silicon a material that the semiconductor industry has been working on for over forty years; it would be really attractive to stay on silicon and also achieve good device matrices that nano-electronics provides. The main objective of this paper is to present Simulation of silicon Nanowire field Effect Transistor (SNWFET) with different oxide having different k value and observe the effect on characteristics thereon using Fettoy Simulator.

(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

1. Introduction Depleted body devices such as FinFETs and Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs have emerged as architectures of choice for technology nodes where conventional planar bulk devices do not provide enough immunity against short channel effects and variability. Offering unsurpassed electrostatic control of the channel, NanoWire FETs (NWFETs)-based architectures are considered as promising successors for future nodes. In all these depleted-body architectures, the control of active power is a strong requirement. Along with supply voltage scaling, it imposes design-level power management strategies, parasitic capacitance reduction and it calls for the use of high-mobility channel materials. For p-type channels, compressively strained silicon germanium alloys (SiGe) are attractive candidates. When depleted-body devices are fabricated on SOI, local germanium enrichment can convert Si to SiGe. This fabrication sequence starts with the growth of an epitaxial SiGe layer, followed by oxidation. During the latter, the surface of the SiGe layer is converted to silicon dioxide while Ge is segregated to the lower part of the stack, which gradually becomes more Ge-rich. This paper discusses the fabrication of SiGe channel for UTBBSOI MOSFETs, FinFETs and NWFETs. It reviews the key points associated to each architecture and critical aspects related to SiGe thermal budget, critical thickness, growth rate control and crystal quality. Results highlight the interest of NWFETs for future technology nodes. 2. SiGe channel UTBB FDSOI MOSFETs The Ge enrichment technique was initially developed for the planar FDSOI architecture and in that context, it was shown that high quality uniform SiGe films can be fabricated by alternating oxidizing and diffusion steps. For a SiGe/Si initial stack of given thickness and composition, the enrichment thermal budget needs to be significantly different when it is performed on SOI or on tensile SOI (sSOI). In the last case, the film initial tensile strain slows Ge diffusion (Fig. 1-a), which can lead to Ge pile up and defect formation if process temperature is too high with respect to the peak concentration (Fig. 1-b). Defect-free SiGe layers can be obtained on sSOI by using longer diffusion steps and reducing process temperature (Fig. 1-c). 3. SiGe-channel FinFET Although Ge enrichment can produce fully-strained layers, the patterning of SiGe blanket film into finite-dimension active areas yields elastic stress relaxation. This feature is particularly attractive for the fabrication of SiGe channel FinFETs where channel configuration results in longitudinal uniaxial compression, which is most favorable to hole transport. However, this processing sequence involves the elaboration of a thick blanket SiGe layer (through Ge enrichment and epitaxial thickening). Even with optimized processing, for a targeted Fin height (SiGe thickness) of 35 nm, significant crystal quality degradation is observed by X-Ray Reciprocal Space Mapping for {113} (RSM) when the Ge fraction approaches 50% (Fig. 2-a), in agreement with literature. To overcome this limit, Ge enrichment of already patterned Si Fins was investigated. This sequence relieves the limits set by SiGe critical thickness in the vertical direction, but it also constricts the pre-enrichment SiGe growth conditions. If SiGe growth rate is strongly dependent on crystal orientation, the final Fin profile is degraded (Fig. 2-b). In contrast, Fin profile can be maintained (Fig. 2-c) when uniform SiGe thickness can be achieved on Fin sidewalls (Fig. 2-d). RSM shows that Fins with up to 50% Ge fraction exhibit no significant relaxation (Fig. 2-e). This approach is expected to be most beneficial for tall Fins. 4. SiGe-channel NWFETs W-gate NWFETs were fabricated in a gate first scheme (Fig. 3-a). This configuration combines the respective benefits of SiGe channel FDSOI MOSFETs and FinFETs in terms of SiGe crystal stability [5] and uniaxial strain. With this and excellent electrostatic integrity, significant mobility gains are demonstrated down to a gate length of 14nm (Fig. 3-b), paving the way for future energy-efficient systems. 5. Acknowledgment Part of these results was obtained in a Joint Development Program between IBM, STMicroelectronics and LETI CEA. Figure 1

Modifying the emission of light from a semiconductor nanowire array

Semiconductor nanowire arrays have been identified as a promising platform for future light emitting diodes (LEDs), for example, due to the materials science freedom of combining lattice-mismatched materials in them. Furthermore, the emission of light from nanowires can be tailored by designing their geometry. Such tailoring could optimize the emission of light to the top side as well as enhance the emission rate through the Purcell effect. However, the possibility for enhanced light extraction from III-V nanowire arrays over a conventional bulk-like LED has not been investigated systematically. Here, we use electromagnetic modeling to study the emission of light from nanowire arrays. We vary both the diameter of the nanowires and the array period to show the benefit of moving from a bulk-like LED to a nanowire array LED. We study the fraction of light emitted to the top air side and to the substrate at wavelength λ. We find several diameter-dependent resonant peaks for which the emission to the top side is maximized. For the strongest such peak, by increasing the array period, the fraction of emitted light that is extracted at the top air side can be enhanced by a factor of 30 compared to that in a planar bulk LED. By modeling a single nanowire, we confirm that it is beneficial to place the nanowires further apart to enhance the emission to the top side. Furthermore, we predict that for a nanowire diameter D &amp;gt; λ/2, a majority of the emitted power ends up in the substrate. Our results offer direction for the design and optimization of nanowire-array based light emitting diodes.

Study of temperature variation on threshold voltage and sub-threshold slope of E $$\delta$$ δ DC MOS transistor including quantum corrections and reduction techniques

For low power System-on-Chip applications, where cost is a critical factor, recently proposed epitaxial delta doped channel (E\(\delta\)DC) structure is a promising alternative architecture within the planar bulk MOS transistor technology due to enhanced electrostatic integrity and reduced threshold voltage variability Sengupta and Pandit (IEEE Trans Electron Dev 63(2):551–557, 2016). In this paper we present a comprehensive analytical and technology computer-aided design (TCAD) simulation study of the effects of variation of temperature on the threshold voltage and sub-threshold slope of an n-type E\(\delta\)DC MOS transistor in the wide range of 100–500 K. We assume Berkeley Short Channel IGFET Model (BSIM) framework for the analytical model. The quantum correction of the threshold voltage is considered while developing the analytical model. The amount of short channel effects at low and high drain bias increase linearly with temperature above 300 K and reduces with reduction in temperature below 300 K. The sub-threshold slope varies linearly with temperature. Another important contribution of this work is that, we also discuss two strategies for reducing the effect of temperature variations on the threshold voltage at the device design level and at the circuit design level.

(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

Due to the unavoidable short channel effects associated with planar bulk silicon MOSFET scaling, FinFET and FDSOI have become the most used solutions for the latest generations of CMOS. Gate control over the channel is excellent and performances are enhanced due to the increased effective width in the case of FinFET [1], and due to the forward body biasing solution in the case of FDSOI. However, after several generations of industrially produced FinFET and FDSOI, one crucial question will arise: how far can those technologies be scaled down? Currently, nanowire (NW) transistors have been proven to be excellent candidates for advanced technology nodes. Specifically, electrostatic control is improved over FinFET for better performance and energy savings. Over the last ten years, many developments on nanowire fabrication and nanowire FETs have been proposed [2] [3] [4] [5]. Today, stacking several nanowires at such scale paves the way for a significant increase in the effective width and current density along with substantial savings in device footprint. Stacked nanowires can be implemented with different geometries such as circular or square cross-sections. However, we recently confirmed [5] among other studies [6] that thin and wide devices, also labelled as nanosheets, provide the best performances with respect to the FinFET technology. A further attractive aspect for the use of nanowires in transistors, is that it may be possible to keep some of the flexibility from the planar technologies. In contrast, FinFET technology imposes a discrete partitioning of the active area. In order to increase the output current of a given FinFET based gate, it may be necessary to add another fin to increase the footprint by one fin pitch. Using nanosheets transistors, channel width can be tuned to obtain the required amount of current with limited impact on footprint as discussed in [7]. Stacked nanowire technology is also appealing as one possible solution due to the fact that their integration can be derived from FinFET. Several groups are currently working on their integration trying to minimize the variations from FinFET Gate-Last process [8]. Two options were identified and labelled as NW first and NW last referring to the fabrication of the NW stack. In the former, several successive epitaxies are performed and patterned to form the active zone as a vertical fin, after which silicon or silicon germanium needs to be removed in order to leave suspended silicon or silicon germanium channels. In the NW last integration, selective removal of silicon germanium happens in between the spacers after the removal of the sacrificial gate. In this case, an etch stop layer must be created to prevent the final gate penetrating under the spacers. This etch stop layer must also be low K in order to recreate the missing spacer material in between the NWs. Due to this requirement, an alternative integration has also been investigated. In the NW first option the selective removal of silicon germanium is done before the first spacer patterning and deposition. This method is also coupled with the use of a hydrogen silsesquioxane (HSQ) resist. This flowable oxide can be exposed through the silicon nanowires and the remaining material left after developing can be used as a sacrificial gate during the gate last process. The spacer deposited afterward is able to wrap around the NWs and the oxide temporary gate. As a consequence, this method provides self-aligned gate and spacer. In recent years, we have also come to focus on carrier transport in NW devices. We have produced several NW-FETs in trigate and Ω-gate shapes on SOI in which we measured electron and hole mobility. Face related transport was observed and improved by using proper strain engineering. Strained SOI and silicon germanium raised source and drain were found to have a significant impact on mobility [4]. Currently, this work is also being integrated in order to boost the performances of our stacked NW-FETs. In this paper we propose a review of the NW architecture and of different integration concepts. Several key points for the performance optimization will be pointed out. [1] Natarajan, S. et al. IEDM, 2014[2] Ernst, T. et al. IEDM 2006[3] Coquand, R. et al. VLSI 2013[4] Barraud, S. et al. VLSI 2013[5] Gaben, L. et al. SSDM 2015.[6] Kim, Seong-Dong et al. S3S 2015[7] Lacord, J. et al. SSDM 2012.[8] Lauer, I. et al. VLSI 2015

Cavity polariton condensate in a disordered environment

We report on the influence of disorder on an exciton-polariton condensate in a ZnO based bulk planar microcavity and compare experimental results with a theoretical model for a non-equilibrium condensate. Experimentally, we detect intensity fluctuations within the far-field emission pattern even at high condensate densities which indicates a significant impact of disorder. We show that these effects rely on the driven dissipative nature of the condensate and argue that they can be accounted for by spatial phase inhomogeneities induced by disorder, which occur even for increasing condensate densities realized in the regime of high excitation power. Thus, non-equilibrium effects strongly suppress the stabilization of the condensate against disorder, contrarily to what is expected for equilibrium condensates in the high density limit. Numerical simulations based on our theoretical model reproduce the experimental data.

A Comparison of the SEU Response of Planar and FinFET D Flip-Flops at Advanced Technology Nodes

Heavy-ion experimental results were used to characterize single-event upset trends in 16 nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data show that 16 nm bulk FinFET flip-flops have considerably lower SEU cross sections than their sub-32 nm planar counterparts for linear energy transfer (LET) less than $10~\hbox{MeV-{cm}}^{2}/\hbox{mg}$ . However, FinFET SEU cross section improvement compared to the planar technologies is weak for high LET particles. Three-dimensional technology computer-aided design simulations are used to investigate charge collection mechanisms and single-event transient (SET) pulse widths at these advanced fabrication nodes. Simulation results show that SETs follow conventional scaling trends, which are that SET pulse widths reduce with technology scaling.

Theoretical analysis of optical mode deflection in lithium niobate waveguide with serrated array electrodes

In this paper, we establish a lithium niobate (LN) thin film planar waveguide and an annealed proton exchange (APE) waveguide model with serrated array electrodes configuration to deflect and reshape the optical mode. The refractive index profile of the waveguide can be electro-optically manipulated by applying an external voltage into the serrated array electrodes. Through the simulation results, it is observed that different refractive index manipulation of LN waveguide can make the optical beam have different deflection and reshaping. The comparison between the thin film and APE bulk planar waveguide is investigated. When the beam deflection is modulated via the high-speed electro-optic effect of LN, the temporal and spatial beam smoothing can be achieved for the application of high power laser system and other optical signal processing.

Toward Ultrahigh Red Light Responsive Organic FETs Utilizing Neodymium Phthalocyanine as Light Sensitive Material

The performance of photoresponsive organic FETs (photOFETs) intimately depends on their optical absorption and charge carrier transport property. We report on red light responsive photOFETs based on various device structures utilizing neodymium phthalocyanine (NdPc2) as the light sensitive material. PhotOFETs based on planar heterojunction, bulk heterojunction (BHJ), and hybrid planar–BHJ (HPBHJ) with NdPc2 and C60 on poly(vinyl alcohol) (PVA) and SiO2 gate dielectric were fabricated and characterized. Among various device structures, HPBHJ-photOFET on PVA dielectric showed the best performance. For the 650-nm-red light illumination, an ultrahigh photoresponsivity of 108 A/W and a maximum photosensitivity of $3.75 \times 10^{4}$ were obtained. The ultrahigh enhancement of the photoresponsivity for HPBHJ-photOFET is resulted from high absorption coefficient of NdPc2 in the red light region, high dissociation efficiency of the photogenerated excitons, and high electron mobility of C60 layer grown on PVA.

Toward Ultimate Scaling of MOSFET

In this brief, we investigate the extendibility of FinFETs and planar bulk devices to 7- and 5-nm technology nodes focusing on electrostatics. At these nodes, the expected contacted device pitch will be in the range of 30–40 nm, requiring the gate length to scale to 12–14-nm range. We show that 6-nm-thick FinFET can scale to these gate lengths while maintaining the equivalent electrostatics as the current 14-nm node high-performance FinFETs. We show that planar bulk devices can scale to the same gate lengths using ultrashallow extension junctions and recessed device channel without aggressive gate insulator scaling and possess electrostatics equivalent to the high-performance planar 22-nm node.

Seebeck Coefficient Enhancement of ALD PbTe/PbSe Nanolaminate Structures Deposited inside Porous Silicon Templates

In this paper, lead chalcogenide based thermoelectric nanolaminate structures were fabricated by alternately depositing PbTe and PbSe ALD layers on regular planar silicon wafers and on microporous silicon templates. Lead bis(2,2,6,6-tetramethyl-3,5-heptanedionato) (Pb(C11H19O2)2), plus (trimethylsilyl) telluride ((Me3Si)2Te) and (trimethylsilyl) selenide ((Me3Si)2Se) were used as the chemical ALD precursors for lead, tellurium and selenium, respectively. The Seebeck coefficient in horizontal direction (parallel direction to the surface) to the multiple layered PbTe/PbSe nanolaminate structures was measured by an MMR Seebeck system, and benchmarked against the Seebeck coefficient in the vertical direction to the sample surface. The results of the Seebeck measurements clearly indicate that the multiple layered PbTe/PbSe nanolaminate structures synthesized by ALD on microporous silicon templates exhibit significantly increased Seebeck coefficients in both horizontal and vertical directions, in stark contrast to the case when the same ALD thermoelectric nanolaminates are grown on regular planar bulk Si substrates.

Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits

In this paper, δ-doped partially insulated junctionless transistor (δ-Pi-OXJLT) has been proposed which shows that, employing highly doped δ-region below the channel not only reduces the off-state leakage current (IOFF) and short channel effects (SCEs) but also reduce the requirements of scaling channel thickness of junctionless transistor (JLT). The comparative analysis of digital and analog circuit performance of proposed δ-Pi-OXJLT, bulk planar (BP) JLT and silicon-on-insulator (SOI) JLT has also been carried out. The digital parameters analyzed in this work are, on-state drive current (ION), IOFF, ION/IOFF ratio, static power dissipation (PSTAT) whereas the analog parameters analyzed includes, transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) of the devices. In addition, scaling behavior of the devices is studied for various channel lengths by using the parameters such as drain induced barrier lowering (DIBL) and sub-threshold swing (SS). It has been found that, the proposed δ-Pi-OXJLT shows significant reduction in IOFF, DIBL and SS over BPJLT and SOIJLT devices. Further, ION and ION/IOFF ratio in the case of proposed δ-Pi-OXJLT also improves over the BPJLT device. Furthermore, the improvement in analog figures of merit, GM, GM/IDS, GMRO and fT in the case of proposed δ-Pi-OXJLT clearly shows that the proposed δ-Pi-OXJLT is the promising device for mixed signal integrated circuits.

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current in saturation with respect to increased temperature and reduced supply voltage explains the increased SEU sensitivity of the flip-flop designs. Experimental SEU cross sections from isotropic Americium-241, 5.4-MeV alpha particle show irradiation increases by 30 × on average, and up to orders of magnitude, as a result of increased device temperature and reduced supply voltage.

Radiation performance of planar junctionless devices and junctionless SRAMs

The objective of this work is to analyze the radiation performance of the planar junctionless devices and junctionless device-based SRAMs. Bulk planar junctionless transistor (BPJLT) and silicon-on-insulator planar junctionless transistors (SOIPJLT) under heavy ions irradiation have been studied using TCAD simulations. 6T-SRAM cells built up of BPJLTs and SOIPJLTs have been investigated for their soft error performance. Even though the bipolar amplification of the SOIPJLT is more compared to BPJLT, the soft error performance of the SOIPJLT SRAM is better compared to BPJLT SRAM.

Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits

Bulk FinFETs have emerged as the solution to short-channel effects at the 22-nm technology node and beyond. The capability of 3-D stacking of dies from various technologies will eventually enable stacking FinFET dies within 3-D integrated circuits. Within 3-D circuits, through silicon vias (TSVs) are a known source of substrate noise in planar bulk technologies. While FinFETs are expected to demonstrate superior noise immunity relative to planar devices due to superior gate control over and volume inversion of the active fin, the impact of TSV noise on FinFETs has not been previously quantified. To evaluate TSV-FinFET noise coupling, we develop in this paper a simulation methodology that extends the state of the art by accurately modeling substrate noise due to digital signals on nearby TSVs and improving the extraction of substrate circuit models from full-wave electromagnetic simulations. To overcome the lack of high-fidelity FinFET SPICE models that accurately capture the effects of substrate noise, we use high-fidelity technology computer-aided design (TCAD) FinFET models. Our results show that FinFETs exhibit an order of magnitude less leakage current noise transients, and two orders of magnitude less saturation current noise transients, relative to comparable planar technologies. Our findings are generalizable, showing that FinFETs are significantly more robust to substrate noise than equivalent planar devices.