Abstract
A set of upset criteria based on circuit characteristic switching time frame is developed and used to bridge transistor-level TCAD simulations to circuit-level single-event (SE) upset cross sections for advanced (fast and small) digital circuits. Interpretation of the measured and 3D TCAD simulated single-event upset (SEU) responses of bulk planar circuits and bulk FinFET circuits using the short-time based upset criteria quantitatively explains the observed divergence of low-LET FinFET cross sections from simple geometric scaling predictions. Comparisons of measured and computed single-event cross section responses show excellent agreement.
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