Performance optimisation of junctionless FET in nano regime using segmented channel - A 3D numerical simulation study

Abstract

The performance of the planar junctionless devices is improved using corrugated substrate also known as SegFET device. Bulk and SOI based planar junctionless devices are investigated for their performance enhancement using 3D numerical simulations. Four devices, (i) BPJLT - junctionless device on bulk planar substrate (ii) BPJL SegFET - junctionless device on bulk corrugated substrate (iii) SOIJLT - junctionless device on SOI planar substrate (iv) SOIJL SegFET - junctionless device on SOI corrugated substrate, are taken for study. BPJL SegFET and SOIJL SegFET devices are compared against BPJLT and SOIJLT devices to find out the benefit of the corrugated substrate in junctionless devices. The parameters ION, IOFF, ION/IOFF ratio and unity gain frequency (fT) are used for comparison. Replacing the planar substrate with corrugated substrate improves the ION/IOFF ratio but degrades fT. The impact of corrugated substrate on bulk device is more compared to SOI device. The impact of VSTI region (WVSTI) and stripe region widths (WSPACE), and permittivity of VSTI region (KVSTI) are also analyzed. While better ION/IOFF performance can be achieved by using higher permittivity in VSTI region and by increasing the VSTI width, higher fT is obtained by using higher stripe width. A full factorial DOE simulation has also been performed in order to rank the above three parameters with respect to ION, IOFF and ION/IOFF at the end. An overall ranking has also been provided which predicts WVSTI to be the most sensitive parameter irrespective of ION, IOFF or ION/IOFF.