Abstract
Junctionless (JL) devices are new generation technology advancement. Numerous research works have been done with focus on several different architectures of strained and unstrained JL devices. In this paper, an effort has been made to give a brief review of strained-JL (S-JL) devices. A review of modeling techniques in such S-JL devices has also been outlined. Unstrained devices have also been reviewed highlighting the need for JL architecture. Simulations have been performed to analyze the enhancement in device performance. The review indicates that this technology is very much required in ultra-short channel devices, where further scaling to improve the transistor density and device functionality have been stretched to their maximum limit. JL devices help to eliminate the need for constructing ultra-abrupt junctions. Advantages of strain in JL MOSFETs are also reviewed. Enhancements of up to 30-40% in ON current has been characterized in such devices. Strained devices also showed improvement in threshold voltage and leakage currents.
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