Planar Bulk Research Articles

Foreword Special Issue on Variation Aware Technology and Circuit Co-Design

Once considered mature and commodity technology, CMOS Si technology keeps revamping itself as a collection of most innovative technologies known to humanity at this given time. Beyond conventional vanilla scale of SiON/Poly planar bulk Si technology, lab-level experiments constantly become manufacturing reality, such as high- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> , metal gate, FDSOI, FinFET, and many exotic patterning technologies. This rapid pace of new technology introduction to CMOS technology, however, requires much more sophisticated optimization of process, device, and circuit design, in order to maximize return on investment. Careful optimization of process technology, device structure, layout, and circuit design in a holistic manner enables significant performance improvement while reducing overall power consumption with the least amount of area penalty.

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula> . Compared with halo doping with the same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{{T,{\rm sat}}}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\rm DD} = 0.8$ </tex-math></inline-formula> V, despite no <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{{\scriptscriptstyle ON}}}$ </tex-math></inline-formula> enhancement, the SPW reduces DIBL by 45% and enhances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\rm EFF}$ </tex-math></inline-formula> by 18%. Compared with halo doping with the same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{{\scriptscriptstyle OFF}}} = 100$ </tex-math></inline-formula> nA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\rm DD} = 0.8$ </tex-math></inline-formula> V, the SPW structure reduces DIBL by 16%, enhances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{{\scriptscriptstyle ON}}}$ </tex-math></inline-formula> by 5%, and improves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\rm EFF}$ </tex-math></inline-formula> by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT) leakage in comparison with halo doping. Otherwise, 20 times larger BTBT leakage will emerge due to the profile overlap between retrograde doping and drain/extension doping.

(Invited) Advanced Semiconductor Devices for Future CMOS Technologies

The future of Moore’s law is not only driven by silicon estate reduction, performance enhancement and cost issues, but also requires a tight control to minimize the overall power consumption. During the last decade the device scaling has been achieved by optimization of process modules, introduction of new materials and modified device concepts. For the front-end part of standard CMOS this leads to the implementation of stress engineering, ultra-shallow junctions, gate-stacks (high-k materials, cap layers, metal gates) with EOT’s below 1 nm, optimization of process sequences (e.g. gate-first versus replacement gate or gate-last), raised source/drain for resistance control, etc. Higher drive currents and better electrostatic control have triggered the exploration of the third dimension by going over to Multi-gate devices (MuGFETs). Parallel to the development of CMOS on bulk silicon substrates, the use of SOI substrates received extensive attention due to the reduced process complexity in addition to enhanced electrical performance. For scaled-down technologies, fully depleted technologies with ultra-thin body and buried oxide (UTBB SOI) have demonstrated their strong potential down to the 14 nm mode (1). At those dimension there exists a strong competition between planar UTBB SOI and bulk FinFETs. Beside changing the gate concept such as in FinFETs, devices with an operation mechanism different from thermionic emission are explored. Tunnel Field Effect Transistors (TFETs) are based on band-to-band-tunneling and allow to achieve subthreshold swings below 60 mV/dec, thereby reducing the power consumption (2). Both horizontal and vertical TFET approaches are emerging as post-CMOS alternatives with a strong potential for future technologies. Further scaling leads to gate-all-around (GAA) and nanowire devices. The quest for higher drive currents triggers beside stress engineering the use of mobility boosters associated with high mobility materials like Ge and III-V. The strong progress made in epitaxial growth techniques resulted in the fabrication of Ge (optimal for p-channel performance), III-V (optimal for n-channel devices) or hybrid Ge/III-V devices on a Si substrate (3). Very good performance has been demonstrated at device level. These high mobility materials are also implemented in TFET and nanowire structures. Near the end of the roadmap the research efforts are focused towards carbon-based materials like carbon nanotubes (4) and graphene (5), spintronics (6), magnetic tunnel junctions and the use of 2D materials such as transition metal dichalcogenides (MX2) like MoS2 and NbSe2(7). For several of these approaches device feasibility has already been demonstrated. This paper analyzes the status and the challenges of several of these advanced CMOS technologies (some of them are illustrated in Fig. 1) and outlines potential limitations for future scaling in view of important electrical parameters such as variability, noise performance and reliability. A technology benchmarking will be given. 1) Q. Liu et al., Techn. Digest IEDM, 228 (2013). 2) A. Ionescu and H. Riel, Nature, 479, pp. 329 (2011). 3) S. Takagi and M. Takenaka, Proc.10thInt,. Conf on Solid-State and Integrated Circuit Technology (ICSICT), 53 (2010). 4) H.-S.P. Wong and D. Akinwande, Carbon nanotubes and graphene device physics, Cambridge University Press, 2011. 5) V. Skakalova and A.B. Kasier, Graphene: Properties, preparation, characterization and devices, Woodhead Publ., Elsevier, 2014. 6) S. Sugahara and J. Nitta, Proc. IEEE, vol. 98, 2124 (2010). 7) F. Schwierz and J. Pezold, Proc. 11thInt,. Conf on Solid-State and Integrated Circuit Technology (ICSICT), 978 (2012). 8) K. Mistry et al., Techn. Dig. IEDM, 274 (2007). 9) C. Claeys et al., Proc. SBMicro 2013, DOI 10.1109/SBMicro.2013.66761851. 10) A. Vandooren et al., Nanoelectronics Workshop, Kyoto, Japan, 21 (2009). 11) J. Mitard et al., Jpn. J. Appl. Phys., 50, 04DC17 (2011). 12) L. Witters et al., Techn. Dig. IEDM, 534 (2013). 13) R. Rooyackers et al., Techn. Dig. IEDM, 92 (2013). 14) N. Waldron , IEEE Electron Dev. Lett., vol. 35, no. 2, 1097 (2014). 15) M. Lemme, T. Echtermeyer, M. Baus, H. Kurz, IEEE Electron Dev. Lett., vol. 28, no. 4, 282 (2007). Figure 1

(Invited) 14nm FDSOI Technology for High-Speed and Energy-Efficient CMOS

As CMOS technology scales down, two paths are pursued by the industry to overcome the fundamental limits of traditional planar bulk transistors. One is the introduction of a Tri-Gate or FinFET transistor at the 22 and 16 nm nodes [1, 2]. These architectures provide impressive drive currents per footprint at low supply voltages because of the 3-D conduction channel and excellent electrostatic control. Conversely, they have high gate and parasitic capacitances, proportional to the 3-D effective W increase, which negatively impacts both the speed and active power consumption. Alternatively FDSOI provides an evolutionary path. First introduced at the 28nm node [3], FDSOI includes excellent mismatch properties, a simplified planar manufacturing process vs 3-D finFET technology and capitalization of existing design techniques. It also extends the possibility of back biasing and therefore offers unique “smart” solutions for dynamic power optimization [4]. The technology presented in this paper furthers the appeal of FDSOI to the 14nm node [5]. Compared to the 28nm technology, new Front-End process elements include a dual SOI/SiGeOI N/P channel, a dual workfunction gate-first HKMG integration scheme and a dual in-situ doped Si:CP/SiGeB N/P raised source-drain [5]. Additionally hybrid bulk areas, formed before Shallow Trench Isolation (STI), provide a space for passive devices and ESD FETs to be built [6]. The strained-SiGe channel (cSiGe) is realized before STI patterning to avoid SiGeOI over-thinning linked to the Ge condensation process at active edges [7] (Fig.1). As shown in Fig.1, strain into the channel has been experimentally measured by Nano-Beam Electron Diffraction (NBED) : 1% compressive strain in the 6nm thin SiGeOI channel (25%Ge) is demonstrated. After gate patterning, a N/P dual spacer/dual epitaxy scheme is used, as illustrated in Fig.2.Since gate-to-drain capacitance (Cgd) is of high importance for the circuit speed and power, spacer, poly thickness and raised source-drain epitaxy (Fig.2) has been optimised to minimize Cgd down to ~0.3fF/µm for both n and pMOS devices. cSiGe and SiGeB source-drain implementation in 14nm FDSOI provides a large pMOS drive current enhancement when compared to FDSOI technology at the 28nm node. As a result of low Cgd and large pMOS drive current, 14FDSOI technology demonstrated in [5] a -20% delay gain with the Fan-Out 3 (FO3) RO inverters at the same static leakage and a 100mV Vdd reduction (0.8V vs 0.9V) over the 28nm FDSOI technology (Fig.3). From this previous work, the transistor performance has further progressed and the delay boost is now established at -34% with -100mV Vdd operation, as shown in Fig.3. It means >50% speed frequency in 14FDSOI at 0.8V Vdd vs 28FDSOI at 0.9V Vdd. These large performance enhancements over 28FDSOI make 14FDSOI as a leading edge technology for the 14nm node and a highly competitive technology for low voltage and energy efficient CMOS applications.

Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability

An ultra-low voltage performance of nanowire-transistors-based SRAM cell is investigated using the SPICE model parameters extracted from measurement data. The impact of S-factor and threshold voltage variations on the static noise margin and the minimum operating voltage is evaluated in nanowire transistor as well as in planar bulk transistor and quasi-planar bulk transistor. The performance benefits of undoped nanowire-transistor-based SRAM are measured in terms of the read stability for low voltage and low off leakage current operation.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on–off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise ( of 10−13–10−11 µm2/Hz for n-type and 10−12–10−10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Uranium reduction on magnetite: Probing for pentavalent uranium using electrochemical methods

Pentavalent uranium is generally treated as an unstable intermediate when uranyl, U(VI)O22+, is reduced to U4+. However, mineral surfaces have been shown to stabilize pentavalent uranium, thus hindering further reduction (Ilton et al., 2005, 2010). The subject of this study is to identify the kinetic pathways that lead to U(V)O2+ being a metastable species. Electrochemical methods provide an in situ approach for the investigation of the intermediate reaction of U(V)O2+ on the surfaces of magnetite. Redox reactions of uranyl ions on particulate (∼3μm) and bulk magnetite surfaces were investigated using cyclic voltammetry and potential step chronoamperometry using cavity microelectrodes and bulk (planar) mineral electrodes. The estimated redox potentials are consistent with the standard redox potential of UO22+/UO2+, indicating UO22+ is first reduced to UO2+ on the surfaces of both powder and bulk magnetite. The one-electron reduction of UO22+ to UO2+ was further confirmed by directly measuring the number of electrons transferred during the reduction process on the bulk magnetite electrode. Based on the charge conservation analysis and the positive correlation between the pH and the peak current for the UO2+ transformation to UO22+, the peak corresponding to the oxidation of U4+ to UO22+ was assigned in the voltammograms of particulate magnetite. The presence of U4+ indicates that the disproportionation of UO2+ (2U(V)↔U(IV)+U(VI)) is occurring on the surface of particulate magnetite within the timeframe of the experiment. The lack of a peak for U4+ in voltammograms for bulk magnetite suggests that the rate of the UO2+ disproportionation reaction is slower on bulk magnetite than that on particulate magnetite. The catalytic property of particulate magnetite surfaces on the disproportionation reaction is explained by its ability to adsorb and desorb protons, which could facilitate the proton-coupled disproportionation reaction of UO2+. This increased catalytic activity and related adsorption and desorption kinetics of protons may be related to the increased number of under-coordinated surface sites near step edges on the magnetite powder.

Manipulating oxygen sublattice in ultrathin cuprates: A new direction to engineer oxides

Abstract

Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation

This paper investigates the impact of terrestrial radiation on soft error (SE) sensitivity along the very large-scale integration (VLSI) roadmap of bulk, FDSOI and finFET nano-scale technologies using the MUSCA SEP3 tool. The terrestrial radiation considered in this work includes neutron, proton, and muon particles and alpha-emitters.The results indicate that protons and muons must be taken into account for ground environments. However, significant differences were observed for bulk, FDSOI and FinFET technologies. The downscaling induces an increase in SEU susceptibility to radiation. An overall analysis indicates that the SER does not increase drastically with technological integration for the three technologies considered. Moreover, the results show that FDSOI and FinFET technologies provide resistance to the ionizing radiation effects due to narrow sensitivity volumes. At the ground altitudes, the total SER ranges from 103 and 104 FIT/Mbit for the planar bulk technology while it ranges from 102 and 103 FIT/Mbit for the FDSOI and FinFET technologies.The results of analyses show that for the avionic altitude, neutron and/or the proton environments induce the main contribution to the total SER, whereas muon and α-SER impacts are negligible. For the 45-nm technological node (all types), the neutron contribution is around 60–70% of the total SER. Concerning the ground altitude, α-SER is the main contribution down to the 28-nm node. Moreover, the results suggest muon-induced upset affects the soft error rate from 32-nm SRAM operated at a nominal supply voltage and has a significant impact for circuits fabricated in smaller process technologies (22-nm and 14-nm). In addition, the results show that the muon impact can be the main contribution at 22-nm and beyond. Future terrestrial error rate predictions will require characterizations of the linear energy transfer (LET) threshold with consideration of muon and/or proton environments.

Extension of Planar Bulk n-Channel MOSFET Scaling With Oxygen Insertion Technology

An experimental and simulation study of short-channel planar bulk nMOSFET performance enhancement achieved with oxygen insertion technology is presented. The benefits of this technology for low-power digital logic circuits make it a promising evolutionary approach to extend bulk MOSFET scaling.

Invited: Scaling Mosfets with Self-Aligned Super-Steep-Retrograde-Well

With aggressively reducing of MOSFET area or IC manufacturing costs, the design space to satisfy both device performance and power consumption requirements becomes very limited. Although strain engineering and high-k/metal gate (HKMG) technique were successfully used to scale planar bulk device down to 28nm technology node, further reduction of gate length requires use of fully depleted channel (FDC) to control short channel effect (SCE). FinFET [1] and UTBB SOI [2] are two typical device structures using FDC. However, significant structural and process changes are involved for both FinFET and UTBB SOI implementations. Super steep retrograde well (SSRW) [3] can be used to reduce depleted depth in the channel of bulk MOSFETs with minor process changes. Two major drawbacks for the devices with SSRW are 1) large band-to-band tunneling (BTBT) or leakage between SSRW and source/drain/extension caused by high doping level and 2) difficult to keep abruptness of SSRW due to large thermal budget used in fabrication process, especially source/drain annealing. To fully take the advantage of state-of-the-art integration flow of all gate last HKMG [4], we propose a new method, called self-aligned SSRW, which forms a SSRW self-aligned to the gate of a bulk MOSFET in replacement gate process. The formation of self-aligned SSRWs can avoid source/drain annealing step and reduce the overlap between SSRW and source/drain/extension. A steep retrograde well can be achieved by a relatively low temperature spike annealing or laser annealing.Self-aligned SSRW CMOS devices have been fabricated on 200mm Si wafers in our lab. In this paper, we will review and report the first self-aligned SSRW nMOSFETs and pMOSFETs with all-last HKMG process. To investigate the SCE control and BTBT effect by SSRW, an asymmetrical device structure, replaced metal spacer gate (RMSG) MOSFET with an asymmetrical SSRW doping is also introduced. The MOSFETs with self-aligned SSRWs show good SCE control and low off current at a gate length of 25 nm. Dramatically improved DIBL and Ion/Ioff characteristics have been achieved when SSRW doping is used to replace the conventional halo doping. It turns out that with self-aligned SSRW drain-to-body leakage is reduced by upto two decades due to reduction of BTBT leakage current between channel and SD/extension. We have demonstrated that the self-aligned SSRW process is simple and fully compatible with state-of-the-art all gate last CMOS technology, promising for device performance improvement and mass production towards scaling of MOSFETs. Simulations and further improvements for bulk and SOI MOSFETs with self-aligned SSRWs are also discussed.[1] C. H. Jan et al., IEDM Tech. Dig., pp. 44-47 (2012)[2] L. Grenouillet et al., IEDM Tech. Dig., pp. 64-67 (2012).[3] Z. Ren et al., IEDM Tech. Dig., pp. 733 – 736 (2005).[4] P. Packan et al., IEDM Tech. Dig., pp. 2841-2844 (2009)

Dislocated Semiconductor Nanowire Heterostructures

The growth of semiconductor nanowires has broadened the range of viable geometries available for defect-free heterostructures. This is primarily because the volumes are so small and their total strain energy is smaller than the cost of inserting misfit dislocations. Thus, systems with large lattice mismatch form axial and core-shell nanowire heterostructures below critical radii without danger of forming dislocations. Testing whether equilibrium models reliably predict the critical geometries in nanowires has been of great interest, extending similar studies for planar interfaces.This talk will show examples of strain relaxation in various semiconductor core-shell nanowire heterostructures where strain relaxation has occurred via dislocations. The types of dislocations observed and the residual strains are evaluated directly using transmission electron microscopy (TEM) as a function of nanowire composition, size, and geometry. Their geometries are compared to theoretical predictions giving insights about likely relaxation mechanisms. Dislocations must nucleate and grow at nanowire interfaces without the help of existing line defects that might exist in a planar substrate. If they form at the surface of the wire they must diffuse or glide to the interfaces. Most dislocations found in core-shell nanowires that have grown along {111} or {0001} directions are edge type and formed likely by diffusing the short distance from the surface to the interfaces. This also explains their highly uniform spacing along the wires. A glide process from the top or bottom of the wire along the interfaces is not as likely since the typical sidewall interface is not a low energy glide plane.Figure 1 shows an example of a bright-field TEM image of a wurzite InAs-GaAs (0001) core-shell nanowire that has relaxed the axial mismatch strain1. In this case there is a clear indication both from the image and the diffraction pattern that there are two lattices present. The fringes in the image and the spacing of spots in the diffraction pattern show that a mismatch of 7% has relaxed along the axial direction equal to the expected lattice mismatch strain of this system. The multiple spots are due to double electron diffraction events occurring in the GaAs shell and InAs core material. Misfit dislocations along the core-shell interfaces are directly visible from the strain fields in the image and from lattice fringes in higher magnification images.Figure 2 shows another TEM example of a relaxed GaAs-GaSb (111) core-shell interface with a set of dislocations visible2. The extra plane of an edge component is indicated by the white lines on the image. The diffraction pattern has double spots with 95% relaxation both axially and radially within this plane. The shell thickness and core radius were 9 nm and 18 nm, respectively, larger than predicted critical geometries for this radius (2 nm shell)3. Wires grown with less then 2 nm shell thicknesses were coherently strained.In the Ge-Si (111) core-shell system the critical thicknesses are 3 nm shells for a 15 nm radius core compared to 1 nm in a bulk planar growth4. Relaxation shows evidence that the mechanism is via glide along {111} planes oblique to the {110} sidewall facets. There remain questions about whether there is a complete dislocation loop on all sidewall interfaces. In some cases, for example GaAs-GaP core-shell, the GaP sidewall thickness is not uniform developing a triangular facet and therefore misfit dislocations are unnecessary on parts of the nanowire. The differences between the group IV and the III-V systems will be discussed.Acknowledgements:We thank our many collaborators including Watkins, Salehzadeh (SFU), Ruda, Savelyev, Blumin (U. Toronto), Dayeh, Picraux (Los Alamos), and Swadener (Aston U.) and are grateful for funding support from NSERC and CFI/BCKDF.

Investigations of varactor depletion capacitance effects of fin field-effect transistor devices

The effects of the depletion capacitance of a varactor between fin field-effect transistor (FinFET) and bulk planar devices are investigated. Fabricated NMOS varactors are characterized and studied. The depletion capacitance of an NMOS varactor in FinFETs is lower than that of the conventional bulk planar one. Thus, the NMOS FinFET varactor provides a larger tuning range (about 10.4 times with respect to minimal capacitance) than the bulk planar one (approximately 3.7 times). The simulation results of the proposed three-dimensional (3D) devices with FinFET and bulk planar varactors show that the depletion layer width of the NMOS varactors in FinFETs is more sensitive to the applied gate voltage than the bulk planar one.

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20-nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3-D simulation. It is found that raised drain-bias can exacerbate threshold-voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold-voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de-correlation of DIBL against threshold-voltage.

Analysis of Random Variations and Variation-Robust Advanced Device Structures

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

(Invited) A Comparison of Device Architecture, Electrical Performance and Process Flow between FinFET and Planar MOSFETs

In this paper, we compared the device architecture, electrical performance between bulk planar, SegFET, UTBB-SOI and FinFET MOSFETs based on TCAD simulation and we also listed the key fabrication process difference between bulk planar and FinFET devices. Results show that FinFET has best short channel effect (SCE) immunity due to its double gate structure. Hence, FinFET device demonstrates best DC performance, which includes Ion/Ioff, Sub-threshold Swing and DIBL. Analyses also show FinFET has best AC performance: smallest delay and dynamic power consumption. Besides some 20nm technology node’s processes, some brand new processes, such as Fin formation, low-k spacer, poly and HK/MG CMP, SiC/SiGe in-situ doping with Ti-silicide and SAC local interconnects, need to be introduced into the FinFET process flow as a necessary cost of achieving the superior performance.

Interplay between efficiency and device architecture for small molecule organic solar cells.

Small molecule organic solar cells (OSCs) have experienced a resurgence of interest over their polymer solar cell counterparts, owing to their improved batch-to-batch (thus, cell-to-cell) reliability. In this systematic study on OSC device architecture, we investigate five different small molecule OSC structures, including the simple planar heterojunction (PHJ) and bulk heterojunction (BHJ), as well as several planar-mixed structures. The different OSC structures are studied over a wide range of donor:acceptor mixing concentrations to gain a comprehensive understanding of their charge transport behavior. Transient photocurrent decay measurements provide crucial information regarding the interplay between charge sweep-out and charge recombination, and ultimately hint toward space charge effects in planar-mixed structures. Results show that the BHJ/acceptor architecture, comprising a BHJ layer with high C60 acceptor content, generates OSCs with the highest performance by balancing charge generation with charge collection. The performance of other device architectures is largely limited by hole transport, with associated hole accumulation and space charge effects.

Monochromatic and Tunable Terahertz Source Based on Nonlinear Optics

Recent progresses made by authors on monochromatic and tunable terahertz (THz) generation based on nonlinear optics are reviewed, including THz parametric oscillation (TPO) and difference frequency generation (DFG). From the technical point of view, we develop extra-and intra-cavity surface-emitted TPO, as well as DFG with QPM-GaAs crystal. From the point of view of mechanism, Cherenkov phase-matching is comprehensively investigated in both bulk crystal and planar waveguide. A novel scheme for cascading enhanced Cherenkov DFG in waveguide is proposed. From the point of view of material, organic crystal 4-N,N-dimethylamino-4'-N'-methyl-stibazolium tosylate (DAST) is utilized as the nonlinear medium.

Improved device variability in scaled MOSFETs with deeply retrograde channel profile

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage (VTH) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, VTH variability impact of RDF on 65nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5mV lower σ-VTH (ΔAVT between two devices is 1.06mV·μm) than conventional planar bulk MOSFETs at the same Ioff level (0.2nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the VTH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to VTH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.

Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors

Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors