Improved device variability in scaled MOSFETs with deeply retrograde channel profile

Abstract

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage (VTH) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, VTH variability impact of RDF on 65nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5mV lower σ-VTH (ΔAVT between two devices is 1.06mV·μm) than conventional planar bulk MOSFETs at the same Ioff level (0.2nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the VTH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to VTH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.