Study of temperature variation on threshold voltage and sub-threshold slope of E $$\delta$$ δ DC MOS transistor including quantum corrections and reduction techniques

Abstract

For low power System-on-Chip applications, where cost is a critical factor, recently proposed epitaxial delta doped channel (E\(\delta\)DC) structure is a promising alternative architecture within the planar bulk MOS transistor technology due to enhanced electrostatic integrity and reduced threshold voltage variability Sengupta and Pandit (IEEE Trans Electron Dev 63(2):551–557, 2016). In this paper we present a comprehensive analytical and technology computer-aided design (TCAD) simulation study of the effects of variation of temperature on the threshold voltage and sub-threshold slope of an n-type E\(\delta\)DC MOS transistor in the wide range of 100–500 K. We assume Berkeley Short Channel IGFET Model (BSIM) framework for the analytical model. The quantum correction of the threshold voltage is considered while developing the analytical model. The amount of short channel effects at low and high drain bias increase linearly with temperature above 300 K and reduces with reduction in temperature below 300 K. The sub-threshold slope varies linearly with temperature. Another important contribution of this work is that, we also discuss two strategies for reducing the effect of temperature variations on the threshold voltage at the device design level and at the circuit design level.