Compact HSPICE model of magnetic tunnel junction based on voltage-driven spin-transfer torque

Abstract

Spin current manipulation of magnetic tunnel junction (MTJ) opens the attractive way for the development of low-power and high-speed spintronic memory devices (SMD) based on this effect for data storage, high-performance logic systems and mobile telecommunication [1]. The influence of the bias-voltage dependence of in-plane and out-of-plane spin-transfer torque (STT) on the switching thresholds plays an important role in the optimization of SMD during the process of technological design [2]. In this work we present a compact model of MTJ that can be integrated in HSPICE electrical simulator using the standard BSIM4 (Berkeley Short-channel IGFET model) model of the nMOS transistor, where the macrospin magnetization dynamics driven by the applied bias voltage is self-consistent with the direct STT calculation in MTJ from the quantum-mechanical tunneling problem in the same electronic circuit. A comparison of current-voltage characteristics of the nMOS (metal-oxide-semiconductor) transistor in the SPICE simulation within BSIM4 model and TCAD (Technology Computer Aided Design) simulation is performed for the standard 130 nm CMOS (complementary-MOS) technology. The results obtained in the simulation of read and write operations in 1T(transistor)-1MTJ magnetoresistive cell based on our HSPICE compact model of MTJ voltage-driven by STT are in good agreement with the phase diagrams of the stability of spin states experimentally measured in the in-plane magnetized MTJs [3].