Band-to-band Tunneling Research Articles

P-Channel TFET Operation of Bilayer Structures With Type-II Heterotunneling Junction of Oxide- and Group-IV Semiconductors

We propose a p-channel bilayer TFET composed of an n-type oxide semiconductor (n-OS)/p-type group-IV semiconductor (p-IV) heterostructure, allowing us to realize both n- and p-channel TFET operations under the same device structure. Here, the p-IV side in the heterostructure has a metal-oxide-semiconductor (MOS) gate-stack that modulates the surface potential of the p-IV MOS interface and controls the band-to-band tunneling (BTBT) current under the p-TFET operation. Technology computer-aided design (TCAD) simulation predicts the p-TFET operation with symmetric electrical characteristics to the n-TFET operation. Moreover, we experimentally demonstrate the p-TFET operation of the n-ZnSnO/p-SiGe bilayer device, fabricated on a SiGe-on-insulator substrate, under Si back-gate operation. In addition, both n- and p-TFET operations are observed in an identical device by using the top- and back-gate electrodes.

Double-Gate Junctionless 1T DRAM With Physical Barriers for Retention Improvement

In this article, a double-gate (DG) junctionless (JL) transistor with physical barriers is proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this topology, the holes are stored in the region blocked by physical barriers constructed by oxides underneath the source and drain regions rather than a potential well formed by n+-p-n+ as in the conventional structures. The proposed topology achieves an elongated retention time ( ${T}_{\text {ret}}$ ) with larger physical barrier thickness ( ${T}_{\text {oxPB}}$ ) and wider barrier offset length ( ${L}_{\text {BO}}$ ) due to a reduction in band-to-band tunneling (BTBT) (during hold “0”) and recombination (during hold “1”). Maximum retention times of ~2.5 s and ~33 ms have been achieved for channel doping of 1019 cm−3 at 27 °C and 85 °C, respectively, with gate length ( ${L}_{g}$ ) of 100 nm at small drain bias ( ${V}_{\text {DS}}$ ) of 1 V during write “1.” Results demonstrate a better gate length scalability and a retention time of ~4 ms at ${L}_{g}$ of 15 nm with thinner Si channel thickness under the gate ( ${T}_{\text {Si}}$ ) and thicker ${T}_{\text {oxPB}}$ . In addition, the effect of temperature on retention time has been analyzed. With optimized ${T}_{\text {oxPB}}$ at ${L}_{g} = {100}$ nm, the retention time decreases due to thermal generation and recombination from ~2.5 s at 27 °C to ~3 ms at 125 °C.

A Novel Germanium-Around-Source Gate-All-Around tunnelling Field-Effect Transistor for Low-Power Applications.

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current () (11.9 A), a low OFF-state current () (A), and a low and steady (57.29 mV/decade), with the OFF-state current increasing by times. The GAS GAA TFET has high potential for use in low-power applications.

Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Continuous device scaling of tunnel field effect transistors (TFET) faces real challenges in low power VLSI applications. Here in this article, the major limitation of TFET i.e. Ambipolar conduction behavior has been thoroughly discussed and remedies to suppress the leakage current (IOFF) has also been investigated. A thin pocket layers is incorporated in source and drain regions separately at Silicon on Insulator (SOI) TFET, keeping supply voltage (VDD) at 0.5 V. The detail analytical modeling of surface potential distribution along the channel, electric field and tunneling current is derived in this paper. Using two-dimensional numerical device simulator, the various designs are modeled and validated with our proposed methodology. Non-local Band-to-Band tunneling (BTBT) is used for simulation purpose. It is observed that a drain pocket actually helps to reduce the ambipolar conduction and provide better drive current (ION) for fast switching. This further improves the ION/IOFF ratio and also results better subthreshold swing (SS) as 27.43mV/decade to optimize the device characteristics.

An improved tunnel field-effect transistor with an L-shaped gate and channel

An improved tunnel field-effect transistor with an L-shaped gate and channel (LLTFET) is proposed herein. The new structure shows an increased ON-current without any change in the overall area in comparison with state-of-the-art structures. The L-shaped gate extends into the substrate and overlaps with part of the source. An N+ pocket located just below the gate facilities tunneling in both the horizontal and vertical directions, which results in the increased ON-current. Three different models are proposed herein to increase the ON-current with the added advantage of simplified fabrication steps. For one of the proposed models, the ON-current is improved by 63% while the OFF-current is reduced to 12.5% compared with an L-shaped gate TFET (LGTFET) described in literature. An optimum model is also proposed, achieving a subthreshold swing of 21.2 mV/decade at 0.05$$V_{\mathrm{gs}}$$. The simulations are performed using Silvaco ATLAS with the nonlocal band to band tunneling (BTBT) model.

Effect of temperature on analog performance of Mg2Si source heterojunction double gate tunnel field effect transistor

Tunnel field effect transistor (TFET) has been recognized as a better candidate to replace Metal Oxide Semiconductor Field Effect Transistor (MOSFET) owing to its competence to achieve subthreshold swing (SS) less than 60 mV/decade and to reduce short channel effects (SCEs). However, certain limitations (low ON current and ambipolar conduction) need to be overcome so as to enhance the performance of TFET. In this paper, source material engineering (SME) is investigated to enhance ION, by replacing the material of the source region of conventional silicon double gate (DG) TFET by a low bandgap material Magnesium Silicide (Mg2Si). It is observed from simulation results that with Mg2Si as a source presented superior performance with reference to ION, Vth, SS, and ION/IOFF ratio as compared to the conventional Si DG-TFET. Further, reliability issues related to the temperature affectability for the electrical/analog performance of the proposed device is investigated for ambient temperature range (200 K to 400 K). The study done for temperature affectability reveals that, Shockley–Read–Hall recombination dominates in the subthreshold region and band to band tunneling (BTBT) mechanism is dominant in superthreshold region. Furthermore, as temperature is elevated from 200 K to 400 K, IOFF shows significant degradation by an order of 106. Also, it is evident that with increase in temperature threshold voltage (Vth) decreases and transconductance (gm) increases. This study will be helpful in achieving the better performance for Mg2Si source DG-TFET implemented in analog applications.

Circuit Level Modeling of Electrically Doped Adenine–Thymine Nanotube Based Field Effect Transistor

We investigate the gate-controlled, electrically doped tunnelling current in Adenine-Thymine heterojunction nanotube-based Field Effect Transistor (FET). This analytical model FET is designed by Density Functional Theory (DFT) and Non-Equilibrium Green's Function (NEGF) based First principle formalisms. It is demonstrated that Band to Band Tunnelling (BTBT) is possible in relaxed Adenine-Thymine heterostructure nanotube. The evaluation of BTBT tunnelling probability to estimate tunnelling current for only ±0.01V applied bias voltage is calculated using Wentzel-Kramers-Brillouin approximation. Electrical doping is introduced to eliminate the probability of fault generation. By keen observation on the shift of energy levels in the band structure, the availability of high transmission co-efficient peaks and current-voltage response we demonstrate the Schottky barrier nature for this geometrically pre-optimized bio-molecular FET. The doping concentration is varied from 0.0001V to 0.1V to achieve a substantially large amount of tunnelling current when the electronic temperature is kept at 300K. The E-k diagram or complex band structure of this heterostructure nanotube ensures its in-direct semi-conducting nature. This is a first attempt to present a circuit-level demonstration using this Adenine-Thymine nanotube-based bio-molecular FET and validate the obtained results with the existing approaches.

A Novel High Schottky Barrier Based Bilateral Gate and Assistant Gate Controlled Bidirectional Tunnel Field Effect Transistor

In this article, we propose a high Schottky barrier source/drain contacts based bilateral gate and assistant Gate controlled bidirectional tunnel field Effect transistor (HSB-BTFET). Different from Schottky barrier (SB) MOSFET which use lower Schottky barrier to produces the thermionic emission current, the proposed HSB -BTFET utilizes higher Schottky barrier to minimize the thermionic emission current and adopts bilateral gate to generate a strong band-to-band tunneling (BTBT) current which works as the conduction mechanism of the forward current. An assistant gate is introduced which efficiently blocks the reverse biased leakage current. Compared to SB MOSFET, HSB-BTFET can realize lower subthreshold swing, much smaller leakage current, higher $\text{I}_{\mathrm{ on}}-{\mathrm{ I}}_{\mathrm{ off}}$ ratio, compared to TFET, it can realize larger forward current. Besides the device symmetry, it's more compatible with MOSFET technology. The function and influence of the Schottky barrier height have been analyzed.

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this article, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET) is used. The structure is designed such that the band-to-band tunneling (BTBT) occurs at the boundary of these dual-material gates, rather than at the source-channel junction. Further, to realize the XNOR function, the gate-source and the gate-drain overlaps are used. The proposed DGTFET-based logic function implementations are able to modulate the current flow as per the required functionality, achieving an ON-state current by OFF-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio of order ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> . Furthermore, it is demonstrated that a CMOS-type XNOR gate can be realized by combining the proposed XNOR and XOR functions in the pull-up and pull-down network, respectively.

Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor

In this paper, using device simulations, we investigate electrical characteristics of a tunnel field-effect transistor (TFET) in which band-to-band tunneling (BTBT) occurs dominantly within the channel, rather than at source-channel junction. The within-channel BTBT is enabled by sharp band-bending induced by the dual material gate (DMG). The work-functions of two metal gates are chosen, such that the surface potential profile exhibits a distinct step at the DMG interface. Consequently, even under equilibrium condition, a high lateral electric field and an abrupt tunneling junction exist at the DMG interface. When a small gate voltage is applied, the inherent lateral electric field aids in creating an abrupt band alignment and obtaining a small tunneling width. As a result, an excellent average subthreshold swing is obtained in the proposed device. We have also investigated scaling of channel lengths in the proposed device and have demonstrated that within-channel tunneling can be exploited for channel lengths of 40nm and above. Furthermore, low drain threshold voltage and suppressed drain-induced barrier lowering can be obtained in the proposed device. Moreover, in contrast to conventional TFETs, electrical characteristics of the proposed device are less susceptible to source doping variations and shift in gate-edge with respect to the source-channel junction.

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunneling (BTBT) rate, and introduce a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current. Simultaneously, to further decrease ambipolar current, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, respectively, where ΦM1 = ΦM3 &lt; ΦM2. Simulation results indicate that DMMG-HJLTFET provides superior performance in terms of logic and analog/RF as compared with other possible combinations, the ON-state current of the DMMG-HJLTFET increases up to 9.04 × 1 0 − 6 A/μm, and the maximum gm (which determine the analog performance of devices) of DMMG-HJLTFET is 1.11 × 1 0 − 5 S/μm at 1.0V drain-to-source voltage (Vds). Meanwhile, RF performance of devices depends on the cut-off frequency (fT) and gain bandwidth (GBW), and DMMG-HJLTFET could achieve a maximum fT of 5.84 GHz, and a maximum GBW of 0.39 GHz, respectively.

Effect of OFF-State Stress on Gate-Induced Drain Leakage by Interface Traps in Buried-Gate FETs

The gate-induced drain leakage (GIDL) current is one of the major leakage sources in a dynamic random-access memory (DRAM) cell transistor. In addition to band-to-band tunneling (BTBT), which causes GIDL in the gate-to-drain overlap region, the generation of interface traps in the gate dielectric increases the GIDL current by trap-assisted two-step tunneling (TATT). In this article, the influence of OFF-state stress on the generation of the interface traps, which deteriorates GIDL, was quantitatively analyzed with charge pumping (CP) characterization method in buried-channel array transistors (BCATs) for DRAM cells. The applied stress increased the GIDL current while simultaneously degrading device performance including such as transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) and ON-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), due to the generation of the interface traps. By using the CP characterization, the interface traps were spatially profiled along the gate-to-drain overlap region in the junction. Trap distribution inside the energy bandgap was also characterized.

Modified Hurkx band-to-band-tunneling model for accurate and robust TCAD simulations

Band-to-Band Tunneling (BTBT) is a non-local process and is responsible for some of the major leakage mechanisms in transistors such as Gate Induced Drain Leakage (GIDL). It is therefore important to include BTBT in Technology Computer Aided Design (TCAD) simulations to properly capture the leakage current. However, due to its non-local nature, BTBT simulation is computationally intensive. Local BTBT models such as Hurkx model can reduce the computation burden but often underestimate the leakage current at large bias. A new modified Hurkx BTBT model for homojunction devices is proposed and showed to match non-local BTBT model well in diode leakage and transistor GIDL simulations. Compared to non-local BTBT model, using the modified Hurkx model, the simulation speed is increased by >6 times in a 3D FinFET IDVG simulation with GIDL.

Influence of Source Stack and Heterogeneous Gate Dielectric on Band to Band Tunneling Rate of Tunnel FET

In this paper, the presence of source stack and heterogeneous gate dielectric material in the structure of an n-channel tunnel FET (TFET) is investigated. P+ type source stack above the source region causes an increase in the electric field which in turn leads to more band bending in the energy band diagram of the proposed structure. Therefore, the effective width of tunneling region decreases and as a result electron Band to Band Tunneling (BTBT) rate enhances. It is also shown that incorporating hetero gate dielectric material can further enhance BTBT rate in the source-channel region and it becomes more intensive as the permittivity of high-k dielectric is increased. The hetero gate structure which is utilized is a combination of SiO2 and a high-k material. Our simulation results indicate that the presence of SiO2 in the drain side minimizes ambipolar current at negative gate voltages. Simulations are performed using Silvaco Atlas TCAD for a channel length of 50 nm using nonlocal tunneling model.

Large Variation in Temperature Dependence of Band-to-Band Tunneling Current in Tunnel Devices

The observation of a significant temperature-dependent variation in the I-V characteristics of tunneling devices is often interpreted as a signature of a trap-assisted-tunneling dominated current. In this letter, we use a ballistic 2D quantum-mechanical simulator, calibrated using the measured temperature-dependent I-V characteristics of Esaki diodes, to demonstrate that the temperature dependence of band-to-band tunneling (BTBT) current can vary significantly in both Esaki diodes and tunnel FETs. The variation of BTBT current with temperature is impacted by doping concentration, gate voltage, possible presence of a highly-doped pocket at the tunnel junction, and material.

Investigating a Dual MOSCAP Variant of Line-TFET With Improved Vertical Tunneling Incorporating FIQC Effect

In this article, we investigate a variant of the line-tunnel FET employing dual MOS–capacitor (MOSCAP) extensions incorporating field-induced quantum confinement (FIQC). Unlike Gate-over-Source (GoSo) TFET having an all-lateral design, dual-MOS (D-MOS) TFET has raised channel/drain regions exhibiting better electrostatics at the 2-D source boundary. At similar dimensions, 2-D-calibrated simulations reveal that under No-FIQC condition, D-MOS exhibits $2.1\times $ better ${I} _{ \mathrm{\scriptscriptstyle ON}}$ along with much improved parasitic leakage in the OFF-state ( ${V} _{ \mathrm{GS}}=\textsf {0}$ V, ${V} _{\textsf {DS}}=\textsf {1}$ V). Energy quantization due to FIQC in the conduction band (CB) near the gate dielectric is captured along with the reshaped carrier density distribution. The delay in the onset of vertical band-to-band tunneling (BTBT), $\Delta {V}_{\textsf {BTBT}}$ shift, and deterioration in ${I} _{ \mathrm{\scriptscriptstyle ON}}$ are also calculated. We later observe that the use of a dual-metal-gate (DMG) and an unequal lateral/vertical oxide thickness as structural improvements further eliminates the parasitic leakage. In addition, with the gate–drain underlap ( ${L} _{\textsf {GD}}$ ) up to 10 nm, a reduction in intrinsic delay is also observed.

Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET.

In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core–shell VNWTFETs. The channel thickness (Tch), the gate-metal height (Hg), and the channel height (Hch) were considered as the design parameters for the optimization of device performances. The designed gate-metal-core VNWTFET exhibits outstanding performance, with an on-state current (Ion) of 80.9 μA/μm, off-state current (Ioff) of 1.09 × 10−12 A/μm, threshold voltage (Vt) of 0.21 V, and subthreshold swing (SS) of 42.8 mV/dec. Therefore, the proposed device was demonstrated to be a promising logic device for low-power applications.

A Transition Metal Dichalcogenide Tunnel FET-Based Waveguide-Integrated Photodetector Using Ge for Near-Infrared Detection

This paper presents a novel approach for the design of a waveguide-integrated photodetector that combines the advantage of atomically thin MoS2 tunnel FET (TFET) with infrared detection capability of Germanium (Ge). The Ge layer acting as a photogate for underlying TFET is optimized to have good optical confinement of guided mode traveling in the SOI rib waveguide. The low-power operation, effective gate control, low OFF-state current, and improved subthreshold characteristics of MoS2 TFET effectively enhance the detector performance for on-chip applications. Due to the high sensitivity of the TFET in the subthreshold region, an addition of the photovoltage to the gate voltage increases the band-to-band tunneling (BTBT) significantly, showing good photoresponse. The analytical and simulation results illustrate that at 1550 nm wavelength with an incident optical power intensity of 3 Wcm−2, a maximum responsivity of 2700 AW−1 and an ON–OFF ratio ( $I_{ON}/I_{OFF}$ ) of 107 is obtained. The device shows good spectral sensitivity with a low dark current.

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 &lt; ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

Si/Ge Hetero Tunnel Field-Effect Transistor with Junctionless Channel Based on Nanowire.

A Si/Ge hetero tunnel field-effect transistor (TFET) with junctionless channel based on nanowire (JLNW-TFET) is proposed, and its electrical performance and dependency of natural parameters are investigated. The JLNW-TFET is operated by compensating each demerit of the following two mechanisms: thermionic generation of junctionless field-effect transistor (JLFET) and band to band tunneling (BTBT) generation of tunnel field-effect transistor (TFET). Although the on-current Ion of JLNW-TFET decreases approximately ten times as much as that of the conventional TFET, its subthreshold swing SS is three times steeper than that of the conventional TFET and ambipolar current Iambipolar does not appear as a result of the structural characteristics. Ioff increases due to Shockley-Read-Hall (SRH) recombination when the density of traps increases; however, an increase in SS is not observed. At temperatures higher than room temperature, Ioff increases slightly and SS and Ion are almost constant. Furthermore, quantum confinement and trap assisted tunneling do not significantly affect the performance of the devices except for increasing Ioff and slightly decreasing Ion.