Abstract
In this paper, the presence of source stack and heterogeneous gate dielectric material in the structure of an n-channel tunnel FET (TFET) is investigated. P+ type source stack above the source region causes an increase in the electric field which in turn leads to more band bending in the energy band diagram of the proposed structure. Therefore, the effective width of tunneling region decreases and as a result electron Band to Band Tunneling (BTBT) rate enhances. It is also shown that incorporating hetero gate dielectric material can further enhance BTBT rate in the source-channel region and it becomes more intensive as the permittivity of high-k dielectric is increased. The hetero gate structure which is utilized is a combination of SiO2 and a high-k material. Our simulation results indicate that the presence of SiO2 in the drain side minimizes ambipolar current at negative gate voltages. Simulations are performed using Silvaco Atlas TCAD for a channel length of 50 nm using nonlocal tunneling model.
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