Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Abstract

Continuous device scaling of tunnel field effect transistors (TFET) faces real challenges in low power VLSI applications. Here in this article, the major limitation of TFET i.e. Ambipolar conduction behavior has been thoroughly discussed and remedies to suppress the leakage current (IOFF) has also been investigated. A thin pocket layers is incorporated in source and drain regions separately at Silicon on Insulator (SOI) TFET, keeping supply voltage (VDD) at 0.5 V. The detail analytical modeling of surface potential distribution along the channel, electric field and tunneling current is derived in this paper. Using two-dimensional numerical device simulator, the various designs are modeled and validated with our proposed methodology. Non-local Band-to-Band tunneling (BTBT) is used for simulation purpose. It is observed that a drain pocket actually helps to reduce the ambipolar conduction and provide better drive current (ION) for fast switching. This further improves the ION/IOFF ratio and also results better subthreshold swing (SS) as 27.43mV/decade to optimize the device characteristics.