Performance Investigation of a Novel Si/Ge Heterojunction Asymmetric Double-Gate DLTFET for Low-Power Analog/RF and IoT Applications

Abstract

The existence of band-to-band tunneling (BTBT) at the tunneling junction, resulting in low OFF-state leakage current (IOFF ) and subthreshold swing (SS) (<60 mV/dec), are the attractive performance measures of tunnel field-effect transistors (TFETs) to replace complementary metal oxide semiconductor (CMOS) technology in the nanometer era. Still, TFET has some impediments, such as low ON-state current (ION ), ambipolar conduction, and fabrication-associated complications, for instance, the necessity of ultrasharp abrupt junctions for BTBT to occur, précised doping regulations, random dopant fluctuations (RDFs), and an indispensable need of exorbitant annealing procedures and high thermal budgets. To deal with these issues, a charge plasma (CP)-based dopingless TFET (DLTFET) has received a great deal of attention as its p+ source and n+ drain are designed by applying the appropriate work function (WF) at the metal electrodes in contact with the intrinsic semiconductor. This DLTFET structure circumvents RDF and issues related to the thermal budget. However, akin to the conventional silicon (Si)-TFET, a low ION is exhibited in the Si-based DLTFET due to the substantially high electron-effective masses for Si and the minor horizontal electric field at the junction. Therefore, a heterojunction DLTFET with an asymmetric double gate (HJ-ADG-DLTFET) is proposed and discussed in this chapter to subdue the limitations of Si-DLTFET. In the proposed device, the heterojunction is created by utilizing a small bandgap semiconductor material (germanium [Ge]) for the source section and a large bandgap semiconductor material (Si) for channel and drain section, which intensifies the BTBT rate at the channel-source junction. Subsequently, an increment of one order for ION has been obtained by HJ-ADG-DLTFET. Furthermore, HJ-ADG-DLTFET has been analyzed parallel to ADG-DLTFET in terms of transfer characteristics (ID -VG ), first-order transconductance (gm 1), gate-to-drain capacitance (Cgd ), cutoff frequency (fT ), gain-bandwidth product (GBP), device efficiency (DE), and transconductance frequency product (TFP). We have also investigated the linearity parameters of the device such as second- and third-order transconductances (gm 2, gm 3), voltage intercept points of the second and third orders (VIP 2, VIP 3), current intercept points of the third order (IIP 3), and third-order intermodulation distortion (IMD3) to provide better insight into the linearity of HJ-ADG-DLTFET. Additionally, along with current-voltage characteristics, the reliability of the device ought to be guaranteed. For reliability analysis, we have carried out interface trap charge (ITC) analysis as well as process, voltage, and temperature (PVT) analysis. In ITC analysis, we have investigated different densities and polarities of trap charges. For PVT analysis, we have carried out gate length variations as the gate length is a process-related parameter, supply voltage alterations from 0.4 V to 1.0 V, and temperature variations from 200 K to 500 K. From these analyses and results, it is inferred that the HJ-ADG-DLTFET is a better substitute for MOSFET for low-power (LP) analog/radiofrequency (RF), linear, and Internet of Things (IoT) applications.