Adder Structure Research Articles

Efficient Boolean-to-Arithmetic Mask Conversion in Hardware

Masking schemes are key in thwarting side-channel attacks due to their robust theoretical foundation. Transitioning from Boolean to arithmetic (B2A) masking is a necessary step in various cryptography schemes, including hash functions, ARX-based ciphers, and lattice-based cryptography. While there exists a significant body of research focusing on B2A software implementations, studies pertaining to hardware implementations are quite limited, with the majority dedicated solely to creating efficient Boolean masked adders. In this paper, we present first- and second-order secure hardware implementations to perform B2A mask conversion efficiently without using masked adder structures. We first introduce a first-order secure low-latency gadget that executes a B2A2k in a single cycle. Furthermore, we propose a second-order secure B2A2k gadget that has a latency of only 4 clock cycles. Both gadgets are independent of the input word size k. We then show how these new primitives lead to improved B2Aq hardware implementations that perform a B2A mask conversion of integers modulo an arbitrary number. Our results show that our new gadgets outperform comparable solutions by more than a magnitude in terms of resource requirements and are at least 3 times faster in terms of latency and throughput. All gadgets have been formally verified and proven secure in the glitch-robust PINI security model. We additionally confirm the security of our gadgets on an FPGA platform using practical TVLA tests.

Implementation of Carry Skip Adder using Carry Select Adder with Improved Area, Delay, and Power Efficiency

This paper presented a Carry Skip Adder (CSKA) structure with less area, less delay, and lower power consumption. This can be achieved with Carry Select Adder's (CSLA) help. The proposed structure uses AND-OR-INVERT (AOI) and OR-AND- INVERT (OAI) compound gates for the skip logic. The use of Carry Select Adder will reduce the number of LUTs used (i.e.) the area of the proposed structure, reduce delay in performing processes, and also reduce power consumption. Simulation of the proposed hybrid CSKA-CSLA structure reveals a reduction in area, delay, and power consumption compared with the CSKA-RCA structure and with the latest works in the field. The simulation results reveal the improvementinareabyreducingthenumberofLUTsfrom91to79 and in delay by reducing the time required to process from 39.969ns to 35. 258ns and power consumption by reducing the power required to process from 64.44 mW to 64.41 mW when compared with the CSKA-RCA structure. This project used the Xilinx ISE tool to simulate the Area and Delay Analysis and the AlteraQuartusI Itool to simulate the Power Analysis.

High energy efficient and configurable CIM macro for image processing

Traditional von Neumann architecture, characterized by separate memory and processing units connected by a limited-capacity memory bus, faces challenges in handling tasks with high energy efficiency requirements. In contrast, the compute-in-memory (CIM) architecture offers a promising alternative, facilitating high parallelism in data processing while integrating storage functions, thereby significantly reducing memory access frequency and power consumption. This study presents a fully digital CIM macro featuring a novel self-write-back 12T cell. This bitcell is capable of performing Boolean logic operations and autonomously writing back results into the in-situ cell, thereby significantly improving energy efficiency.This can be used for binary logical operations between each pixel of two images without requiring additional storage area. A bidirectional read/write architectural design enables matrix transposition. This can achieve image rotation.Additionally, this novel 12T cell also offers the option to choose not to write back the results of logical operations, thereby providing the flexibility and configurability for image processing. Combined with an adder tree, it enables multiply-and-accumulate (MAC) operation for convolutional neural networks(CNNs). This can be used for feature extraction. We propose an 18T full adder structure with lower power-delay product than current state-of-the-art full adders, which is advantageous for improving the synthesis performance of the adder tree.The CIM macro supports a 4-bit × 4-bit MAC operation. The proposed CIM macro, designed and simulated using a 28 nm CMOS process with a 16 Kb static random access memory (SRAM), demonstrates promising results. At VDD = 0.9 V, the logic operation energy consumption is 1.35 fJ/bit with an energy efficiency of 740TOPS/W, and MAC operation energy consumption is 15.91 fJ/bit with an energy efficiency of 62.85 TOPS/W.

Implementation of Systolic Multiplier Using Hybrid Multiplexer Dependent Adder

Multipliers are basic building blocks in various integrated circuits like microprocessors, micro controllers, and ALUs. The existing multipliers suffer from high power consumption and inefficient use of hardware resources. They often rely on traditional adder structures that are not tailored for specific operations, leading to suboptimal performance. Additionally, their fixed architectures limit adaptability and scalability in different applications. So, the proposed approach offers enhanced computational efficiency and reduced power consumption compared to conventional multiplier designs. By integrating multiplexer-dependent adders into the systolic array, the proposed method optimizes resource utilization and delivers improved performance for various arithmetic operations. This integration allows for dynamic selection of adder types based on the specific multiplication operation, significantly reducing power consumption and latency. By adapting the hardware resources to computational needs, the method achieves higher efficiency and flexibility, making it suitable for a wide range of applications in digital signal processing and data processing systems.

A new ripple carry adder structure based on a swing‐boosted full adder for concurrent error correction in low‐resolution pipeline analog‐to‐digital converters

SummaryA ripple carry adder (RCA) structure is presented which can concurrently correct a gain error in low‐resolution pipeline analog‐to‐digital converters (ADCs). The RCA is composed of a new swing‐boosted full adder (FA) based on the transmission gate (TG) technique. So, it is low‐power, high‐speed, and full‐swing with high driving capability. In 90 nm technology, the results of power, delay, and power‐delay‐product (PDP) of the FA are 1.5296 μW, 2.1141 ns, and 3.2337 fJ, respectively. The RCA with an area of 408.09 μm2 is evaluated by a 3‐bit pipeline ADC with 1.5‐bit per stage. When the erroneous codes are passed through the RCA, the maximum and minimum integral nonlinearity (INL) are improved by 19.83% and 90.98%, while the maximum and minimum of the differential nonlinearity (DNL) are improved by 50%, and 42.06%, respectively.

Performance optimized approximate multiplier architecture ST-AxM - based on statistical analysis and static compensation

In this study, our primary aim is to develop a highly efficient multiplier architecture tailored for approximate computing, with a specific focus on optimizing power efficiency. Multiplication constitutes a fundamental operation in computing, profoundly impacting applications ranging from signal processing to artificial intelligence. The emerging paradigm of approximate computing seeks to enhance hardware design by balancing computational accuracy with power consumption. Our objective is to achieve this balance by implementing a novel multiplier architecture employing several key methods. We aim to harness a smart and adaptable partial product reduction technique grounded in statistical analysis to reduce adder usage, incorporate power-efficient adder structures, and introduce static error compensation mechanisms to maintain lower error levels. Our methodology involves analyzing various multiplier hardware architectures, developing the proposed approximate multiplier architecture, and rigorously validating its performance against a state-of-the-art truncation multiplier. We utilize Xilinx ISE for synthesis to obtain results pertaining to area efficiency and power efficiency. Furthermore, we employ error metrics to comprehensively compare the performance of our proposed architecture with existing designs. Finally, we assess the practical applicability of these different multipliers by integrating them into an image sharpening application and evaluating metrics such as Peak Signal to Noise Ratio (PSNR) and Similarity Index (SI). Our results indicate that the statically truncated approximate multiplier outperforms existing designs by being 18 % more area-efficient and 5 % more power-efficient, all while maintaining acceptable error levels. Moreover, in the context of image processing, it demonstrates PSNR and SI values closely aligned with those of standard fixed-point multipliers. In conclusion, our innovative approximate multiplier architecture, grounded in statistical analysis and static compensation, offers substantial improvements in area and power efficiency, rendering it suitable for error-tolerant applications such as digital signal processing and image processing.

Efficient and low-cost approximate multipliers for image processing applications

The image processing can be implemented in an error-tolerant mode with acceptable accuracy. In digital image processing, the adders and multipliers are the most important components. In this paper, two approximate multipliers based on an approximate 4:2 compressor and two 4-bit full adders with minimizing computational costs are proposed. The first and second proposed approximate multipliers are designed by using the proposed imprecise 4-bit full adders and 4:2 compressor, respectively. In the structure of the proposed multipliers, we have adders for the addition of two multiple-bit numbers. In the adder structure, the full adders are designed based on two modified half adders and one NAND gate. The proposed approximate 4:2 compressor and two approximate 4-bit full adders are compared from hardware and accuracy point of view such as gate count, area-delay product (ADP), error rate (ER), mean error distance (MED), mean relative error distance (MRED), and normalized error distance (NED). The efficacy of proposed multipliers in image processing applications such as image multiplication is evaluated using MATLAB. The results show the proposed approximate multipliers are comparable in terms of area, delay, and mean structural similarity index metric (MSSIM) parameter with other works.

A Novel High Computing Power Efficient VLSI Architectures of Three Operand Binary Adders

Directly or indirectly adders are the basic elements in almost all digital circuits, three operand adders are the basic building blocks in LCG (Linear congruential generator) based pseudo-random bit generators. Elementary adders are fast, area and power efficient for small bit sizes. Carry save adder computes the addition in O(n) time complexity, due to its ripple carry stage. Parallel prefix adders such as Han-Carlson compute the addition in O(log(n)) time complexity but at the cost of additional circuitry. Hence new high-speed power-efficient adder architecture is proposed which uses four stages to compute the addition, which consumes less power, and the adder delay decreases to O(n/2). Even though it is not much faster than the High-speed Area efficient VLSI architecture of three operand adders (HSAT3), it computes the addition by utilizing less power. The proposed architecture is implemented using Verilog HDL in Xilinx 14.7 design environment and it is evident that this adder architecture is 2 times faster than the carry save adder and 1, 1.5, 1.75 times faster than the hybrid adder structure for 32, 64, 128 bits respectively. Also, power utilization is 1.95 times lesser than HSAT3, 1.94 times lesser than the Han-Carlson adder, and achieves the lowest PDP than the existing three operand techniques.

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

AbstractThis research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures.

Design of Multiplier Circuit Using Carry Save Adder Based on Quantum-Dot Cell Automata

The executions of various complex models reliant on quantum-dot cell automata (QCA) are of high eagerness for investigators. So far, the structure of complex adders in QCA is focused on bringing down clock delay, cell count, and logic gates. This paper proposes the circuit format of a 4-bit multiplier utilizing a carry save adder (CSA) and its implementation on QCA. The CSA is framed with another QCA design of the full adder circuit. The CSA gives preferable expansion strategies over Brent–Kung (BK) adder and Landler–Fisher (LF) adder. This multiplier represents fewer cell counts and clock delays conversely with past designs.

A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation

In the nano-scale era, quantum-dot cellular automata (QCA) technology has become an appealing substitute for transistor-based technologies. QCA will be the preferred technology for developing the next generation of digital systems. On the other hand, the full-adder and ripple carry adder (RCA) are the crucial building blocks of complex circuits, the most used structures in digital operations systems, and a practical part of the most well-known complex circuits in QCA technology. In addition, this technology was used to design the full adder for several procedures, like multiplication, subtraction, and division. For this reason, the full adder is generally investigated as a central unit and microprocessor in developing QCA technology. Furthermore, most previous QCA-based adder structures have suffered from some drawbacks, such as a high number of cells, high energy consumption, the high number of gates, and the placement of inputs and outputs in a closed loop; hence, the implementation of an efficient adder with only one gate and a low number of cells, such as exclusive-OR (XOR) gate, can solve all previous problems. Therefore, in this paper, a significantly improved structure of 3-input XOR is suggested based on the promising QCA technology. In addition, a QCA clocking mechanism and explicit cell interaction form the foundation of the proposed QCA-based XOR gate configuration. This gate can be easily converted into an adder circuit while containing a small number of cells and being extremely compressed. The suggested QCA-based XOR design is focused on optimizing a single-bit adder using cellular interaction. The suggested single-bit adder contains 14 cells. Based on this adder, several different RCAs, such as 4, 8, 16, and 32-bit, are designed. The comparison of the proposed single-bit adder to the best coplanar and multi-layer ones shows a 51.72% and 36.36% reduction of cells, respectively. In addition, all suggested designs are verified through simulation using QCADesigner and QCAPro. Finally, many physical validations are provided to approve the functionality of the suggested XOR design.

Mitigation of Critical Delay in the Carry Skip Adders Using FinFET 18nm Technology

In this paper optimization of full adder in 3-dimensional (3-D) using Fin Field Effect Transistor (FinFET) with Gate Diffusion Input (GDI) is proposed to optimize critical delay, power. FinFET technology is more suitable for below 10nm technology process. The major aim of this work is to indemnify significant factor in adder structure i.e. critical delay. Pipelining architecture is enforced to accomplish the objective with the aid of FinFET 18nm technology. The structure is optimized to get the minimum delay confinement. Suggested design needs less logic resources. The outcomes are validated using FPGA synthesis methods. By applying the FinFET technique, we developed adder topology yielding up to 90% performance improvement with respect to delay, power and area compared to the conventional adders. The simulation was carried out with low power cds ff mpt PDK. The study also includes a carry skip adder design for FPGA implementation.

Design of Low Power and Process Control Hybrid Adder with Complemented Carry Structure

A Hybrid logic style is most popular when compared to other logic styles in implementation of full adder circuits. Conventional hybrid adder uses truth table with true form of carry in and carry out. This will result in non-identical outputs of sum and carry for about 75% of the input combinations. Alternate truth table has been proposed to increase the similarity of sum and carry outputs. In this paper, circuit is designed for complemented carry in and complemented carry out of full adder. This novel structure allowed to design 20-T hybrid adder with process control, low power and low power delay product. The proposed adder structure is applicable for ripple carry adder. The performance of the designs is measured by simulating it in tanner T-spice environment using 0.25um technology. Proposed design has also been implemented up to 64-bit for its scalability. All the results were taken at several operating frequencies with varying word size of the adder. The proposed adder minimizes the power by 9.5%-51.5% and the power delay product by 3%-60% when compared to its counterparts for N-bit adder.

The Design of Digital System with CSA

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and ORAND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode

In this paper, two accuracy configurable adders capable of operating in approximate and exact modes are proposed. In the adders, which include a block-based carry propagate and a parallel prefix structure, the carry chains are cut off in the approximate mode limiting the carry chain depth to two blocks. In the case of parallel prefix adder, we propose a special carry generate tree equipped with a power gating means. In both of the proposed structures, the critical paths of the adders are not increased in the exact operating mode. Thus, the main objective of proposing these approximate adder structures is to present an accuracy configurable adder structure whose delay in the exact mode is almost the same as an exact adder. The efficacies of the proposed accuracy configurable adders are compared with some state-of-the-art adder structures using a 15nm CMOS technology. In addition, their efficacies are evaluated in two error-resilient applications. These studies show that the proposed carry-propagate adder has 22% (51%) lower energy consumption (error rate) compared to the best prior works. Also, the proposed parallel prefix adder provides, on average, 20% lower energy consumption compared to the exact parallel prefix adders.

Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Adders are used in processing units such as Arithmetic and Logic Units (ALUs) as an essential building block, and in many blocks of microprocessor chips critical path, adders occupy an important place. Hence reducing power, area and increasing the speed of adders are significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with a reduction in consumption of power and area without affecting the speed when compared with the conventional adder structures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes, and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time, which further reduces the voltage with the parallel structure. Experimental results show that the 32-bit implementation of the proposed adder has a significant power reduction of 42% and 38.3%, area reduction of 27%, and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5-tap FIR filter which shows a significant reduction in power consumption and area.

A High-Performance Full Adder Design with Low Area, Power and Delay

A new one-bit adder architecture is described that may be used with a variety of logics, including Static CMOS, transmission gates, the Transmission Full Adder (TFA), and the New-14T Gate Diffusion Input Method (GDI). The Modified Gate Diffusion Input Method (MGDI) is used to suggest a novel structure design for a full adder. The full adder circuit is used in the Modified Gate Diffusion Input Method (MGDI), and experimental results demonstrate its superior performance compared to traditional methods. Full adders with multistage arrangements are also considered, as their performance may differ from that of a 1-bit full adder. As a result, two applications of multistage full adder structures, the ripple carry adder (RCA) and 6:2 compressor are used to analyze the findings. The power, area and delay are reduced by around 40% when compared to the existing methods. All the designs are simulated using Tanner EDA. The proposed full adder has a lower transistor count (6 or 7 transistors), lower power dissipation, and less delay than previous designs, according to simulation data.

A General Methodology to Optimize Flagged Constant Addition

Addition is a ubiquitous operation frequently carried out in most computing applications. Traditionally, three-operand addition is done using either two adders or a carry–save adder. However, there exist applications such as digital signal processing, image processing, floating point arithmetic, etc. wherein among the three operands, one is constant. For such cases, we propose a flagged constant addition methodology, applicable to any constant, to compute the result with the least area, delay and power. The resulting architecture is referred to as general constant flagged adder (GCFA). We propose an Optimized Constant Generation (OCG) algorithm and a Hardware Optimization Algorithm (HOA) to achieve hardware-efficient constant flagged adder. These two algorithms are designed to lower the computational complexity. The OCG algorithm accepts the constant to be added and converts it into an optimized constant. This optimized constant then forms the input to the HOA where the hardware modifications are performed. Unlike the proposed work, the existing flagged adder structures do not provide a general methodology to obtain the optimized constant and hardware for all the constants, resulting from the presence of architectural customization for all constants and word lengths. Exhaustive hardware analyses have been carried out to prove the efficacy of the proposed architecture against the existing designs. Structural Verilog code is synthesized for each to obtain the area, delay and power. Synthesis results show up to 35.85% and 49.24% reductions in area–delay and power–delay products, respectively. The improved speed and lower hardware requirements make the proposed methodology a suitable choice for constant addition.

Performance Investigation of a Modified Hybrid Parallel Prefix Adder for Speedy and Lesser Power Computations

Achieving high speed and lesser power in large operand adders is greatly necessitated for incorporating modern portable systems, which are highly demanded in the artificial intelligence sector, especially in deep learning-based applications. Conventional speedy adder structures are based on parallel-prefix (PP) types that have huge power consumption. The modified design is deemed the key solution for contemporary demands in today's modern consumer electronics. The existing hybrid adder (HA) architecture functions on the basis of the framework, in which the least significant carriers are produced in large PP adders quicker than the most-significant ones. The base concept of this HA is to customize the binary to Excess-1 Converter (BEC) and make C in = 1 in the standard Carry Select Adder (CSA) to reduce power and area than RCA. The key improvement in BEC is minimizing the logic gate counts that are necessitated than FA of n-bit architecture. In the existing KS-RCA, the customized BEC is introduced for achieving considerable performance metrics improvement. All existing work and the proposed adder implementation are done in Cadence tool RTL compiler with 90 nm TSMC technologies using the dynamic power verification and analysis methods of RTL. The proposed technique efficiently diminishes the delay that is 76.39% lesser than the CSEL-BEC , 70.86% lesser than CSEL-RCA, and significantly 3.27% lower than the KS-RCA. Also, power consumption is reduced up to 28.92%, 10.61%, and 11.06% than the existing methods, such as KS-RCA, CSEL-RCA, and CSEL-BEC, respectively. However, the area is efficiently reduced by the proposed method up to 29.52% concerning the maximum value of implemented techniques.

High-Speed Adder Design Space Exploration via Graph Neural Processes

Adders are the primary components in the data-path logic of a microprocessor, and thus, adder design has been always a critical issue in the very large-scale integration (VLSI) industry. However, it is infeasible for designers to obtain optimal adder architecture by exhaustively running EDA flow due to the extremely large design space. Previous arts have proposed the machine learning-based framework to explore the design space. Nevertheless, they fall into suboptimality due to a two-stage flow of the learning process and less efficient nor effective feature representations of prefix adder structures. In this article, we first integrate a variational graph autoencoder and a neural process (NP) into an end-to-end, multibranch framework, which is termed the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">graph neural process</i> . The former performs automatic feature learning of prefix adder structures, whilst the latter one is designed as an alternative to the Gaussian process. Then, we propose a sequential optimization framework with the graph NP as the surrogate model to explore the Pareto-optimal prefix adder structures with tradeoff among Quality-of-Result (QoR) metrics, such as power, area, and delay. The experimental results show that compared with state-of-the-art methodologies, our framework can achieve a much better Pareto frontier in multiple QoR metric spaces with fewer design-flow evaluations.