Implementation of Carry Skip Adder using Carry Select Adder with Improved Area, Delay, and Power Efficiency

Abstract

This paper presented a Carry Skip Adder (CSKA) structure with less area, less delay, and lower power consumption. This can be achieved with Carry Select Adder's (CSLA) help. The proposed structure uses AND-OR-INVERT (AOI) and OR-AND- INVERT (OAI) compound gates for the skip logic. The use of Carry Select Adder will reduce the number of LUTs used (i.e.) the area of the proposed structure, reduce delay in performing processes, and also reduce power consumption. Simulation of the proposed hybrid CSKA-CSLA structure reveals a reduction in area, delay, and power consumption compared with the CSKA-RCA structure and with the latest works in the field. The simulation results reveal the improvementinareabyreducingthenumberofLUTsfrom91to79 and in delay by reducing the time required to process from 39.969ns to 35. 258ns and power consumption by reducing the power required to process from 64.44 mW to 64.41 mW when compared with the CSKA-RCA structure. This project used the Xilinx ISE tool to simulate the Area and Delay Analysis and the AlteraQuartusI Itool to simulate the Power Analysis.