Design of Low Power and Process Control Hybrid Adder with Complemented Carry Structure

Abstract

A Hybrid logic style is most popular when compared to other logic styles in implementation of full adder circuits. Conventional hybrid adder uses truth table with true form of carry in and carry out. This will result in non-identical outputs of sum and carry for about 75% of the input combinations. Alternate truth table has been proposed to increase the similarity of sum and carry outputs. In this paper, circuit is designed for complemented carry in and complemented carry out of full adder. This novel structure allowed to design 20-T hybrid adder with process control, low power and low power delay product. The proposed adder structure is applicable for ripple carry adder. The performance of the designs is measured by simulating it in tanner T-spice environment using 0.25um technology. Proposed design has also been implemented up to 64-bit for its scalability. All the results were taken at several operating frequencies with varying word size of the adder. The proposed adder minimizes the power by 9.5%-51.5% and the power delay product by 3%-60% when compared to its counterparts for N-bit adder.