Performance Investigation of a Modified Hybrid Parallel Prefix Adder for Speedy and Lesser Power Computations

Abstract

Achieving high speed and lesser power in large operand adders is greatly necessitated for incorporating modern portable systems, which are highly demanded in the artificial intelligence sector, especially in deep learning-based applications. Conventional speedy adder structures are based on parallel-prefix (PP) types that have huge power consumption. The modified design is deemed the key solution for contemporary demands in today's modern consumer electronics. The existing hybrid adder (HA) architecture functions on the basis of the framework, in which the least significant carriers are produced in large PP adders quicker than the most-significant ones. The base concept of this HA is to customize the binary to Excess-1 Converter (BEC) and make C in = 1 in the standard Carry Select Adder (CSA) to reduce power and area than RCA. The key improvement in BEC is minimizing the logic gate counts that are necessitated than FA of n-bit architecture. In the existing KS-RCA, the customized BEC is introduced for achieving considerable performance metrics improvement. All existing work and the proposed adder implementation are done in Cadence tool RTL compiler with 90 nm TSMC technologies using the dynamic power verification and analysis methods of RTL. The proposed technique efficiently diminishes the delay that is 76.39% lesser than the CSEL-BEC , 70.86% lesser than CSEL-RCA, and significantly 3.27% lower than the KS-RCA. Also, power consumption is reduced up to 28.92%, 10.61%, and 11.06% than the existing methods, such as KS-RCA, CSEL-RCA, and CSEL-BEC, respectively. However, the area is efficiently reduced by the proposed method up to 29.52% concerning the maximum value of implemented techniques.