An area optimized Carry Select Adder

Abstract

In arithmetic operation, adder is the basic hardware unit. So adder performance affects the overall system-performance. Carry Select Adder (CSLA) is widely used in many data processors for high speed application and in digital circuits to perform arithmetic operations. The Regular Square root (SQRT) CSLA consumes more area due to the presence of two Ripple Carry Adders (RCA) in the structure. To optimize the area of Regular SQRT CSLA, one of the RCAs was replaced by a Binary to Excess-1 Converter (BEC) though at the cost of slight increase in delay. Many such improvements have lead to design variety of SQRT CSLAs by using Common Boolean Logic(CBL), First Addition Logic(FAL), Add-one circuit, Modified Reduced Logic Block(MRLB) etc to achieve optimization in terms of area, delay and power. This work proposes a new design comprising of RCA with Cin=0 and a New Logic (NL) for Cin=1 to reduce the area as compared to the Regular SQRT CSLA and Modified SQRT CSLA using BEC. The proposed design is synthesized and simulated in Xilinx ISE design suite 14.2 and is implemented on Spartan 3E XC3S1600E-5-FG484 FPGA device. The comparison shows how the proposed SQRT CSLA is better than the existing regular SQRT CSLA and SQRT CSLA using BEC. The speed of proposed model is also enhanced for higher number of bits than the SQRT CSLA with BEC model.