High energy efficient and configurable CIM macro for image processing

Abstract

Traditional von Neumann architecture, characterized by separate memory and processing units connected by a limited-capacity memory bus, faces challenges in handling tasks with high energy efficiency requirements. In contrast, the compute-in-memory (CIM) architecture offers a promising alternative, facilitating high parallelism in data processing while integrating storage functions, thereby significantly reducing memory access frequency and power consumption. This study presents a fully digital CIM macro featuring a novel self-write-back 12T cell. This bitcell is capable of performing Boolean logic operations and autonomously writing back results into the in-situ cell, thereby significantly improving energy efficiency.This can be used for binary logical operations between each pixel of two images without requiring additional storage area. A bidirectional read/write architectural design enables matrix transposition. This can achieve image rotation.Additionally, this novel 12T cell also offers the option to choose not to write back the results of logical operations, thereby providing the flexibility and configurability for image processing. Combined with an adder tree, it enables multiply-and-accumulate (MAC) operation for convolutional neural networks(CNNs). This can be used for feature extraction. We propose an 18T full adder structure with lower power-delay product than current state-of-the-art full adders, which is advantageous for improving the synthesis performance of the adder tree.The CIM macro supports a 4-bit × 4-bit MAC operation. The proposed CIM macro, designed and simulated using a 28 nm CMOS process with a 16 Kb static random access memory (SRAM), demonstrates promising results. At VDD = 0.9 V, the logic operation energy consumption is 1.35 fJ/bit with an energy efficiency of 740TOPS/W, and MAC operation energy consumption is 15.91 fJ/bit with an energy efficiency of 62.85 TOPS/W.