High-Speed SRAM with Flexible Read/Write Data Width Tailored for Convolutional Neural Network

Abstract

This paper discusses the design of a high-speed Static Random Access Memory (SRAM) which is tailored for convolutional neural network (CNN). Training process of CNNs requires memory to be accessed with different data widths, of which the most popular data widths are from 1 byte to 4 bytes. Traditional SRAMs have a set read/write data width and thus can only read/write one byte at a time. This slows down the training process of CNNs. SRAMs have become one of the bottlenecks of CNNs training speed. We proposed an SRAM with a new architecture that can read/write at flexible data widths. It can read/write any data from 1 byte to 4 bytes. This allows multiple bytes of data to be accessed each clock cycle and increases the memory access speed up to 4 times compared to traditional SRAMs. This can greatly improve the CNN training speed. A 1 KB traditional SRAM and another 1 KB SRAM based on the proposed architecture are also designed and simulated to further verify our design concepts. Power overhead and layout area overhead are also analyzed between the proposed SRAM architecture and the traditional SRAM.