Adder Structure Research Articles

Area Efficient High Speed Vedic Multiplier

Very large scale integration is a process of integrating hundreds of thousands of transistors or devices into a single chip. VLSI can be categorized into two fields Frontend and Backend. Digital VLSI design falls under the Frontend design. Multiplication is an arithmetic operation important for the Digital Signal Processing (DSP) and for processors. Multiplier is the main hardware block for the digital circuit. More than 70% of the applications in a digital circuit are either addition or multiplication. As these operations dominates most of the execution time so we need fast multipliers. The overall objective of a good multiplier is to have high speed, low power consumption unit, less area. Vedic multipliers are the fast multipliers and occupy less area. They are based on the Vedic mathematics sutra "Urdhava-Triyakbhyam" . The paper contain a high speed multipliers and use of different adder structures.

Efficient and high‐throughput application‐specific integrated circuit implementations of HIGHT and PRESENT block ciphers

In this study, low-cost and high-throughput hardware implementations of the HIGHT (HIGh security and lightweigHT) and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo 2 8 . In the proposed structure for implementation of this modular adder, the authors used the structure of Ladner-Fischer, Han-Carlson, Kogge-Stone and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80-bit and 128-bit, the S-box is implemented based on an area-optimised combinational logic circuit. In the proposed S-box structure, the number of logic gates and critical path delay is reduced by using Karnaugh mapping and further factorisation. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. Implementation results of the proposed architectures in 180 nm complementary metal-oxide-semiconductor technology for different unroll factors are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to other related works.

A New Coplanar Design of Multiplier Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) nanotechnology is emerging as a replacement technique for maintaining increasing microprocessor performance and it yields small size, high speed, and low power consumption. On the other hand, a multiplier is a circuit that multiplies two binary values for performing sequential addition operations and accumulating the results. This type of circuit is the basic structural unit of many arithmetic logical units, digital signal processing, and communication system. The multiplier circuit contains some full adders that can perform add operations, so, it is very important that low-complexity full adders are used. Therefore, in this paper, a new 2 × 2 array multiplier circuit in QCA by employing an efficient structure of full adder is designed and implemented. This design is constructed using coplanar layouts and compared its performance with existing QCA multipliers. The operation and efficiency of the proposed structure have been confirmed using QCADesigner tool. The simulation results have demonstrated that the 2 × 2 multiplier leads to less cell count and area as the prime designing factors.

Analysis on Circuit Metrics of 1-Bit FinFET Adders Realized using Distinct Logic Structures

Objective: To compare and analyse different FinFET full adder circuits by varying the temperature. Method/Analysis: A 1-bit full adder is designed using various logic styles and the performance of these adders are compared over a range of temperature values. 32nm FinFET Predictive Technology Model (PTM) is used for designing purpose. Various logic design styles utilised are Complementary Metal-Oxide Semiconductor (CMOS) logic, Transmission Gate (TG) logic, Complementary Pass-Transistor (CPTL) logic, Gate Diffusion Input (GDI) logic. Cadence Virtuoso and Spectre are used for designing and simulation purpose, respectively. Findings: The performance of these adders are analysed based on key circuit metrics like static power, dynamic power, leakage power, delay and power delay product (PDP). On comparison, it is evident that the GDI based adder consumes less leakage power. Also, the propagation delay and power delay product is very less in GDI adder. Novelty/Improvements: The simulation results prove that the GDI adder structure outperforms other structures in sub nanometer technology. This advantage makes GDI technology suitable for realisation of combinational circuits. Future research in digital circuits can be carried out by using GDI technology for designing low power and compact integrated circuit design. Keywords: Complementary Pass-Transistor, Delay, FinFET, Gate Diffusion Input, Leakage Power, Low Power Adder, Transmission Gate, CMOS

High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers

In this paper, low-cost and high-throughput hardware implementations of the HIGHT and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo 28. In the proposed structure for implementation of this modular adder, we used the structure of Ladner-Fischer, Han-Carlson, Kogge-Stone, and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80-bit and 128-bit, the S-box is implemented based on an area-optimized combinational logic circuit. In the proposed S-box structure, the number of logic gates and critical path delay are reduced by using the simplification of the Algebraic terms. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. We implemented glitch filtering on hardware structures of the HIGHT and PRESENT block ciphers based on the latch-based method to reduce the power consumption. Also, the power analysis, timing attacks and hardware-based countermeasures based on an experimental setup are performed. It is claimed that the current and power profiles are unified and there will be no power consumption difference when encryption operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX50 and Spartan-3 XC3S200 FPGAs for different unroll factors are achieved. The results show the structures are robust against attacks and improvements in terms of execution time, throughput and throughput/area compared to others related works.

Delay and Energy Efficient Modular Hybrid Adder for Signal Processor Architectures

In this modern era, high-performance energy efficient devices/systems are the basic requirement for most of the real-time applications. Multiply-accumulate (MAC) units are the frequently used elements in majority of the signal processing architectures. In an MAC unit adders are the basic components. To this end, delay and energy efficient modular hybrid adders for various bit widths are presented. The adder structures are obtained by combining the concatenation and the incrementation schemes to a hybrid structure consisting of modified forms of ripple, carry look ahead, and carry skip adder sections so as to improve delay and energy efficiency. Two versions of hybrid adder architectures are proposed. For n-bit addition, the first adder architecture consists of m numbers of k-bit modified hybrid carry look ahead adder modules, k-bit final sum logic (FSL) stages and output fast carry logic (OFCL) stages. The second adder structure is obtained from the first adder structure by replacing FSL with modified FSL. The speed of addition is improved by the quick and parallel generation of end carry of concatenated adder stages by the modified look ahead carry generation blocks and by the transmission of carries through the modified carry skip action performed by the OFCL blocks. Cadence software with gpdk standard libraries of 45, 90 and 180 nm technology nodes are used for the design and implementation. The values of delay, PDP, and ADP obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency.

High‐throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers

SummaryIn this paper, high‐throughput and flexible hardware implementations of the SIMON and SPECK lightweight block ciphers are presented. The most complex block in the SPECK algorithm is addition modulo 2n, where n is word size (half of the input data). In the proposed structure of modular adder, we used the Sklansky adder, which is an efficient parallel prefix adder with low critical path delay and suitable hardware resources. In the SIMON block cipher, to reduce critical path delay, we use a tree structure for implementation of XOR operations. In addition, we proposed flexible structures that can perform various configurations of the SIMON and SPECK ciphers to support variable key sizes (128, 144, 192, and 256 bits) and block sizes (64, 96, and 128 bits). Therefore, the flexible architectures provide versatile implementations with adaptive security level and the ability of encryption of longer messages based on variable key size and variable block size. Implementation results of the proposed structures in 180 nm CMOS technology for different key and block sizes are achieved. The results show that the proposed structures have better critical path delay compared with other's related works.

Optimal performance of 16-bit acyclic adders of binary codes

The conducted studies established the prospect for enhancing the performance of computing components, specifically, combinational 16-bit adders, based on the use of the principles of computation of digital signals of an acyclic model. The application of an acyclic model for the synthesis of 16-bit parallel adders is designed for: – the process of sequential (for lower bits) and parallel (for all other bits) computation of the sum and carry signals. Thanks to this approach, it becomes possible to reduce eventually the complexity of the hardware part without increasing the circuit depth; – fixation (planning) of the adder circuit depth before its synthesis. This makes it possible to use the logical structure of transitive carry, which ensures the optimal adder circuit depth and does not increase its complexity. Utilizing an acyclic model for the construction of 16-bit parallel adders is more beneficial in comparison with the analogs by the following factors: – the lower cost development, since an acyclic model determines a simpler structure of a 16-bit adder; – application of the latest developed logical structures of transitive carry, which makes it possible to decrease the delay of sum and carry signals, area, power consumption and to increase overall efficiency of 16-bit adders of binary codes. Due to this, the possibility of obtaining optimal values of structure complexity and the depth of the adder circuit is ensured. In comparison with the analogs, it provides an increase in quality of indicator of 16-bit acyclic adders, such as power consumption, chip area by 15–27 %, depending on the chosen structure, and performance by 10–60 %. There are some grounds to argue about the possibility of enhancing the performance of computing components, specifically, 16-bit adders of binary codes by using the principles of computation of digital signals of an acyclic model.

Designing energy-efficient imprecise adders with multi-bit approximation

Since early 2000s, achieving significant energy-efficiency for CMOS VLSI circuit design has become more difficult. Approximate computing is a hopeful solution for enhancing power-efficiency in error-tolerant applications. In such systems, adders play an essential role and mainly contribute to the system's total power and area consumption. Many proposals have been introduced in the literature that build large adders while using novel low power full adder structure as its building blocks. However, single-bit structure approximation, only limits the design space of approximate adders. And leads to a poor trade-off between accuracy and power dissipation. This paper proposes a novel approach for design of multi-bit adders, based on three novel approximate 2-bit adder circuits. Simulation results demonstrates that the proposed adders consume less area and power than the state-of-the-art approximate adders. Up to 80% power improvements are attainable for the proposed designs as compared with the baseline adders.

Carry save adder and carry look ahead adder using inverter chain based coplanar QCA full adder for low energy dissipation

Quantum-dot cellular automata (QCA) technology offers the potential option for performing transistor-less calculations at the nanoscale. In this paper, we introduce a new full adder structure using an inverter chain on a single layer. By utilizing the proposed full adder structure, we design and implement a carry save adder and carry look-ahead adder. Some of these techniques like pipeline structures or asynchronous timing becoming more attractive and are gaining more attention than other solutions. This paper mainly focuses on the high circuit density and energy-efficient aspects of QCA circuits. The design exploits the inherent pipeline nature of QCA, which can lead to an enormous reduction in area using an inverter chain since all computations can be computed in a single block. A comparison among our results and typical structures shows that the presented structures outperformed the best existing designs with respect to area, latency, and cell count. Our structures are more suitable elements for realizing complex QCA circuits with very high operating speed. Functional verification and energy consumption analyses were conducted by well known tools.

CNTFET-Based Design of Ternary Arithmetic Modules

Multiple-valued logic such as ternary logic has attracted the digital system designers attention in recent years as it offers the benefits of reduced interconnects, higher operating speeds and smaller chip area. A goal of multi-threshold circuit design could be easily achieved by incorporating the scalable threshold voltage values of carbon nanotube field effect transistors (CNTFETs). This paper proposes a novel design of low-power and high-performance ternary adder and subtractor circuit design by combining the futuristic ternary and conventional binary logic design approaches. The simplified design of ternary to a binary decoder based on negative ternary inverter and positive ternary inverter outputs, and further transmission gate-based ternary multiplexer implementation facilitates the low power consumption and energy efficiency in the implementation of the complex arithmetic circuits. Extensive HSPICE simulations are conducted with the standard 32 nm CNTFET technology in order to evaluate the performance metrics of the realized circuits. According to the simulation results, proposed ternary adder and subtractor cells show the significant improvement in energy consumption (PDP) as compared to their counterparts under different test conditions. Moreover, the ripple adder structure is realized using the proposed adder circuit in order to test the practicability of given circuits in cascaded structures.

An Efficient Implementation of Hybrid Carry Select Adder Using Parallel Prefix Addition and Binary to Excess 1 Conversion

One of the fastest adder architecture among the prevailing adder architectures. Adders are digital logic devices that add binary numbers together. They are commonly used as a component in an Arithmetic Logic Unit which itself is a component in Central Processing Unit. As a result any electronic device that has a Microcontroller or a CPU such as smart thermostats, digital alarm clock, digital wrist watches, and digital bathroom scales etc use adder circuit. In this work, we present an 8 bit hybrid Carry Select Adder architecture. It employs Parallel prefix addition using Kogge stone adder structure, Brent Kung adder structure, Han Carlson Adder structure and Ladner Fischer adder structures. It also employs Binary to Excess 1 code converter along with parallel prefix adders. Affirmation of the suggested design completed using Verilog code and simulated using Xilinx ISE 14.7 and the power, area and delay results were calculated using Cadence software. Comparisons with existing conventional adder architecture certify its better quality. The experimental analysis probes that the recommended hybrid carry select adder results threefold advantages in regards with speed, area and power.

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

ABSTRACTThis paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS.

High Performance Error Tolerant Adders for Image Processing Applications

In this paper, we proposed High Performance Error Tolerant Adders (HPETA) which have an efficient design and quality metrics for inexact computing applications. To achieve high performance, Multiplexer Based Approximate Full Adders (MBAFA) are proposed in the inaccurate part of the HPETA design. High speed, energy and area efficiency have been achieved by the critical path delay reduction and the number of gate-level logic reduction. The performances of the proposed MBAFA and HPETA are investigated by comparing its speed, area, power and accuracy parameters with those of other existing error tolerant adder structures. The investigation of these designs is performed in the Cadence Encounter software using the Application Specific Integration Circuits (ASIC) TSMC 90-nm technology library. From the Simulation results, the proposed MBAFA-I based HPETA-I adder exhibits high speed, area efficiency, low power consumption, less Area-Delay Product (ADP) and 56.25%, 47.98%, 37.58%, 34.03%, 39.32% lesser Power-Delay Product (PDP) than the existing conventional CSLA, SAET-CSLA, ETCSLA, HSETA, HSSSA, respectively.

Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

Investigations on performance metrics of FINFET based 8- bit low power adder architectures implemented using various logic styles http://www.indjst.org/index.php/indjst/article/view/111071 1489988072

Objectives: To reduce the leakage power dissipation and minimize the propagation delay, a Fin FET based 8-bit adder architecture is constructed. The performance metrics of these structures are calculated over a range of temperatures and are compared with the MOSFET based 8-bit adder architecture. Various logic styles are utilized for constructing the adder. Method/Analysis: A Ripple carry adder structure is employed. The existing adder architecture is constructed using 90nm MOSFET technology. The proposed adder architecture is constructed using 32nm FINFET technology. The various logic styles employed are Complementary Metal-Oxide Semiconductor logic (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate logic (TG) and Gate Diffusion Input logic (GDI). Cadence Virtuoso is used for designing purpose and simulation is performed using Spectre. Findings: Key performance metrics like static power, dynamic power, leakage power, delay and power delay product are calculated. The dynamic power of MOSFET architecture ranges from 7.42µW to 882.6µW. The dynamic power of FINFET architecture ranges from 0.407nW to 156.2nW. The static power (inputs at high logic level) of MOSFET architecture ranges from 0.001µW to 945.76µW. The static power (inputs at high logic level) of Fin FET architecture ranges from 0.725pW to 170.4nW. The static power (inputs at low logic level) of MOSFET architecture ranges from 0.94nW to 1.68mW. The static power (inputs at low logic level) of Fin FET architecture ranges from 0.127pW to 305.3nW. The leakage power (inputs at high logic level) of MOSFET architecture ranges from 1.27nW to 134.7µW. The leakage power (inputs at high logic level) of Fin FET architecture ranges from 0.36pW to 24.77nW. The leakage power (inputs at low logic level) of MOSFET architecture ranges from 0.54nW to 139.9µW. The leakage power (inputs at low logic level) of Fin FET architecture ranges from 0.15nW to 227.6nW. The delay of MOSFET architecture ranges from 0.344µs to 0.46µs. The delay of Fin FET architecture ranges from 0.19µs to 0.28µs. The power delay product of MOSFET architecture ranges from 2.66 to 405.99. The power delay product of Fin FET architecture ranges from 0.83 to 29.67. Novelty/Improvements: The FINFET adder architecture proved to be effective in reducing the propagation delay and leakage power dissipation. This may find usage in high performance devices like microchips and supercomputers. Keywords: Complementary Pass-transistor Logic, Gate Diffusion Input, Low Power Adder, Transmission Gate, CMOS, FINFET

A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA

Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined radix-3 SDF FFT method has been designed. It has less area and large power consumption and delay. In order to overcome these problems, modified carry select adder structure is used to perform the adder operation for reducing the power consumption and delay. Finally, the MCSLA is integrated into radix-3 SDF FFT processor. The hardware complexity and execution time for implementing radix-3 FFT algorithm can be reduced than other FFTs.

General modular adder designs for residue number system applications

Modular adders are very crucial components in the performance of residue number system-based applications. Most of the work published so far has been restricted to modulo (2 n ± 1) adders or modulo-specific adders. Less work has been dedicated to modulo-generic adders. This work presents new designs for modulo (2 n ± K) adders, where K is any integer in the range of 3 ≤ K <; 2 n-1 . The proposed structure merges two binary adder structures and maximises sharing of components, wherever possible. This merger permits shorter cell-interconnections, which results in space wastage reduction. Additionally, tristate-based multiplexers (MUXs) are used in lieu of the more demanding gate-based MUXs. As examined over a very practical range of n, 7 ≤ n ≤ 15, and based on a 65 nm VLSI realisation, the circuit layouts of the proposed adders outperform considerably the most recent and competitive functionally identical published works. On average, the proposed designs have shown reductions in area, time, power, and energy of 23.7, 13.8, 22.9, and 33.6%, respectively.

Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess – 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent – Kung (BK), Ladner – Fischer (LF) and Kogge – Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.

A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis

Quantum-dot cellular automata (QCA) is the appearance of new technology and can be a suitable alternative to semiconductor transistor technology. In this paper, the new structure of the two-input XOR gate is presented, which is the modified version of the three-input XOR gate. This structure can be used to design various useful QCA circuits. By utilizing this gate, we design and implement a new full adder structure with 90-degree cells. This structure is designed in a single layer without cross-wiring. The operation of the proposed structure has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared the effectiveness of our structure with the two previous structures.