Analysis on Circuit Metrics of 1-Bit FinFET Adders Realized using Distinct Logic Structures

M Aalelai Vendhan

doi:10.17485/ijst/2019/v12i26/145499

Abstract

Objective: To compare and analyse different FinFET full adder circuits by varying the temperature. Method/Analysis: A 1-bit full adder is designed using various logic styles and the performance of these adders are compared over a range of temperature values. 32nm FinFET Predictive Technology Model (PTM) is used for designing purpose. Various logic design styles utilised are Complementary Metal-Oxide Semiconductor (CMOS) logic, Transmission Gate (TG) logic, Complementary Pass-Transistor (CPTL) logic, Gate Diffusion Input (GDI) logic. Cadence Virtuoso and Spectre are used for designing and simulation purpose, respectively. Findings: The performance of these adders are analysed based on key circuit metrics like static power, dynamic power, leakage power, delay and power delay product (PDP). On comparison, it is evident that the GDI based adder consumes less leakage power. Also, the propagation delay and power delay product is very less in GDI adder. Novelty/Improvements: The simulation results prove that the GDI adder structure outperforms other structures in sub nanometer technology. This advantage makes GDI technology suitable for realisation of combinational circuits. Future research in digital circuits can be carried out by using GDI technology for designing low power and compact integrated circuit design. Keywords: Complementary Pass-Transistor, Delay, FinFET, Gate Diffusion Input, Leakage Power, Low Power Adder, Transmission Gate, CMOS

Highlights

Power consumption and operation speed are the most decisive factors for any circuit design
Key circuit metrics like dynamic power, static power, leakage power and delay were calculated for every 25°C change in temperature (-25°C to 125°C)
The Gate Diffusion Input (GDI) logic adder provides 74%, 98.4% and 99.5% reduction in dynamic power when compared to the Complementary Metal-Oxide Semiconductor (CMOS), CPTL and Transmission Gate (TG) logic design respectively

Summary

Introduction

Power consumption and operation speed are the most decisive factors for any circuit design. Transistors designed using FinFET technology are used for reducing the leakage power as they provide better control over the channel and allow minimal current to leak through the body during cut-off state. A 1-bit low power adder was designed in[2], which made use of inverter, multiplexer and an XOR gate in 45nm FinFET technology. QFinFET displayed high gate capacitance and had a reduced leakage power dissipation. Delay and power were reduced by 55% and 28% respectively Another pioneering technique of adder design is discussed in[6], where an 8-bit ripple carry adder was designed in 90nm MOSFET technology and 32nm FinFET technology. Various circuit design techniques like TG, CMOS, CPL and GDI logic were used. Key circuit metrics like Dynamic power, Leakage power, Static power, Delay and Power delay product are measured

Implementation using Cadence Virtuoso

Simulation Results and Discussion

Conclusion