Investigations on performance metrics of FINFET based 8- bit low power adder architectures implemented using various logic styles http://www.indjst.org/index.php/indjst/article/view/111071 1489988072

Abstract

Objectives: To reduce the leakage power dissipation and minimize the propagation delay, a Fin FET based 8-bit adder architecture is constructed. The performance metrics of these structures are calculated over a range of temperatures and are compared with the MOSFET based 8-bit adder architecture. Various logic styles are utilized for constructing the adder. Method/Analysis: A Ripple carry adder structure is employed. The existing adder architecture is constructed using 90nm MOSFET technology. The proposed adder architecture is constructed using 32nm FINFET technology. The various logic styles employed are Complementary Metal-Oxide Semiconductor logic (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate logic (TG) and Gate Diffusion Input logic (GDI). Cadence Virtuoso is used for designing purpose and simulation is performed using Spectre. Findings: Key performance metrics like static power, dynamic power, leakage power, delay and power delay product are calculated. The dynamic power of MOSFET architecture ranges from 7.42µW to 882.6µW. The dynamic power of FINFET architecture ranges from 0.407nW to 156.2nW. The static power (inputs at high logic level) of MOSFET architecture ranges from 0.001µW to 945.76µW. The static power (inputs at high logic level) of Fin FET architecture ranges from 0.725pW to 170.4nW. The static power (inputs at low logic level) of MOSFET architecture ranges from 0.94nW to 1.68mW. The static power (inputs at low logic level) of Fin FET architecture ranges from 0.127pW to 305.3nW. The leakage power (inputs at high logic level) of MOSFET architecture ranges from 1.27nW to 134.7µW. The leakage power (inputs at high logic level) of Fin FET architecture ranges from 0.36pW to 24.77nW. The leakage power (inputs at low logic level) of MOSFET architecture ranges from 0.54nW to 139.9µW. The leakage power (inputs at low logic level) of Fin FET architecture ranges from 0.15nW to 227.6nW. The delay of MOSFET architecture ranges from 0.344µs to 0.46µs. The delay of Fin FET architecture ranges from 0.19µs to 0.28µs. The power delay product of MOSFET architecture ranges from 2.66 to 405.99. The power delay product of Fin FET architecture ranges from 0.83 to 29.67. Novelty/Improvements: The FINFET adder architecture proved to be effective in reducing the propagation delay and leakage power dissipation. This may find usage in high performance devices like microchips and supercomputers. Keywords: Complementary Pass-transistor Logic, Gate Diffusion Input, Low Power Adder, Transmission Gate, CMOS, FINFET