High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers

Abstract

In this paper, low-cost and high-throughput hardware implementations of the HIGHT and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo 28. In the proposed structure for implementation of this modular adder, we used the structure of Ladner-Fischer, Han-Carlson, Kogge-Stone, and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80-bit and 128-bit, the S-box is implemented based on an area-optimized combinational logic circuit. In the proposed S-box structure, the number of logic gates and critical path delay are reduced by using the simplification of the Algebraic terms. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. We implemented glitch filtering on hardware structures of the HIGHT and PRESENT block ciphers based on the latch-based method to reduce the power consumption. Also, the power analysis, timing attacks and hardware-based countermeasures based on an experimental setup are performed. It is claimed that the current and power profiles are unified and there will be no power consumption difference when encryption operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX50 and Spartan-3 XC3S200 FPGAs for different unroll factors are achieved. The results show the structures are robust against attacks and improvements in terms of execution time, throughput and throughput/area compared to others related works.