Abstract
The conducted studies established the prospect for enhancing the performance of computing components, specifically, combinational 16-bit adders, based on the use of the principles of computation of digital signals of an acyclic model. The application of an acyclic model for the synthesis of 16-bit parallel adders is designed for: – the process of sequential (for lower bits) and parallel (for all other bits) computation of the sum and carry signals. Thanks to this approach, it becomes possible to reduce eventually the complexity of the hardware part without increasing the circuit depth; – fixation (planning) of the adder circuit depth before its synthesis. This makes it possible to use the logical structure of transitive carry, which ensures the optimal adder circuit depth and does not increase its complexity. Utilizing an acyclic model for the construction of 16-bit parallel adders is more beneficial in comparison with the analogs by the following factors: – the lower cost development, since an acyclic model determines a simpler structure of a 16-bit adder; – application of the latest developed logical structures of transitive carry, which makes it possible to decrease the delay of sum and carry signals, area, power consumption and to increase overall efficiency of 16-bit adders of binary codes. Due to this, the possibility of obtaining optimal values of structure complexity and the depth of the adder circuit is ensured. In comparison with the analogs, it provides an increase in quality of indicator of 16-bit acyclic adders, such as power consumption, chip area by 15–27 %, depending on the chosen structure, and performance by 10–60 %. There are some grounds to argue about the possibility of enhancing the performance of computing components, specifically, 16-bit adders of binary codes by using the principles of computation of digital signals of an acyclic model.
Highlights
Computer industry creates more and more productive computing components using integrated circuits (IC)
The optimal logical structure that implements the condition of transitive carry of unity to higher bits in the circuit of the acyclic 16-bit adder of binary codes ensures the least depth of the adder circuit
Such structures make it possible to perform fixation of the adder circuit depth before its synthesis, which eventually enables a decrease in the general complexity of hardware of the digital component
Summary
Computer industry creates more and more productive computing components using integrated circuits (IC). The improvement of IC parameters, including the performance of its operation, power consumption and temperature mode continue to be a relevant task for designing and technology of manufactu ring integrated circuits. Binary adders are among the most important elements in processor chips, ALU, counters, methods of memory addressing, as a part of the filter, for example, the filter of DSPgrid, etc For this reason, the addition operation is the most commonly used operation in digital circuits. This paper deals with the architecture of the 16-bit pa rallel acyclic adder (PAA) [1, 2] It presents the latest designed logical structures of transitive carry, which make it possible to reduce the delay of sum and carry signals, area, power and improve the overall efficiency of digital components.
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