Performance optimized approximate multiplier architecture ST-AxM - based on statistical analysis and static compensation

Abstract

In this study, our primary aim is to develop a highly efficient multiplier architecture tailored for approximate computing, with a specific focus on optimizing power efficiency. Multiplication constitutes a fundamental operation in computing, profoundly impacting applications ranging from signal processing to artificial intelligence. The emerging paradigm of approximate computing seeks to enhance hardware design by balancing computational accuracy with power consumption. Our objective is to achieve this balance by implementing a novel multiplier architecture employing several key methods. We aim to harness a smart and adaptable partial product reduction technique grounded in statistical analysis to reduce adder usage, incorporate power-efficient adder structures, and introduce static error compensation mechanisms to maintain lower error levels. Our methodology involves analyzing various multiplier hardware architectures, developing the proposed approximate multiplier architecture, and rigorously validating its performance against a state-of-the-art truncation multiplier. We utilize Xilinx ISE for synthesis to obtain results pertaining to area efficiency and power efficiency. Furthermore, we employ error metrics to comprehensively compare the performance of our proposed architecture with existing designs. Finally, we assess the practical applicability of these different multipliers by integrating them into an image sharpening application and evaluating metrics such as Peak Signal to Noise Ratio (PSNR) and Similarity Index (SI). Our results indicate that the statically truncated approximate multiplier outperforms existing designs by being 18 % more area-efficient and 5 % more power-efficient, all while maintaining acceptable error levels. Moreover, in the context of image processing, it demonstrates PSNR and SI values closely aligned with those of standard fixed-point multipliers. In conclusion, our innovative approximate multiplier architecture, grounded in statistical analysis and static compensation, offers substantial improvements in area and power efficiency, rendering it suitable for error-tolerant applications such as digital signal processing and image processing.