65nm Technology Research Articles

A Synthetic Ultra-Wideband Transceiver for Millimeter-Wave Imaging Applications.

In this work, we present a transceiver front-end in SiGe BiCMOS technology that can provide an ultra-wide bandwidth of 100 GHz at millimeter-wave frequencies. The front-end utilizes an innovative arrangement to efficiently distribute broadband-generated pulses and coherently combine received pulses with minimal loss. This leads to the realization of a fully integrated ultra-high-resolution imaging chip for biomedical applications. We realized an ultra-wide imaging band-width of 100 GHz via the integration of two adjacent disjointed frequency sub-bands of 10-50 GHz and 50-110 GHz. The transceiver front-end is capable of both transmit (TX) and receive (RX) operations. This is a crucial component for a system that can be expanded by repeating a single unit cell in both the horizontal and vertical directions. The imaging elements were designed and fabricated in Global Foundry 130-nm SiGe 8XP process technology.

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage and power consumption causes the components that are functioning by the battery for a long period to be washed-out rapidly. In this research, the reversible logic gate-based 9T static random access memory (SRAM) is designed in 14nm FinFET technology to reduce leakage power consumption in memory related applications. The Schmitt-trigger (ST)-based 9T SRAM cell is designed to attain high read-write stability and low power consumption using a single bit line structure. The reversible logic gates of Feynman (FG) and Fredkin gate (FRG) are combined to develop a row and column decoder in an SRAM design to diminish the leakage power. Moreover, the transistor stacking effect is applied to the proposed memory design to reduce the leakage power in active mode. The proposed reversible logic and transistor stacking based SRAM design is implemented in Tanner EDA Tool version 16.0. It also performs both read and write operations using the proposed circuit. The performance measures of read access time (RAT), write access time (WAT), read, write, and static power by varying supply voltage and temperature, delay and stability analysis (read/write static noise margin) are examined and compared with existing SRAM designs.

4-channel, 224Gb/s PAM-4 optical transmitter with group delay compensation in 130-nm BiCMOS technology

4-channel, 224Gb/s PAM-4 optical transmitter with group delay compensation in 130-nm BiCMOS technology

Efficient implementation of a DSIG-JLT-based multiplexer and demultiplexer using different logic styles at 20-nm technology

Efficient implementation of a DSIG-JLT-based multiplexer and demultiplexer using different logic styles at 20-nm technology

High-speed and energy-efficient asynchronous carry look-ahead adder.

Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders.

Design and implementation of a Low power Adder Circuit Using LECTOR Technique

This work implements a 1-bit FA circuit with the CMOS logic with XOR-XNOR combinations. For sum and carry, pass transistors are used to generate the output by combining with XOR, XNOR and CMOS design, and the optimised full adder is implemented with the help of LECTOR technique to control the leakage power. As scaling of CMOS technology has shown improvement in the speed but the leakage power are left to act as major effect. low power VLSI is a new discipline in which high power consumption is becoming an important criteria. But when refers to battery life, high power dissipation is not recommended for device applications. It affects performance, raises cooling expenses, and shortens battery capacity. The switching, dynamic and leakage power changes the inputs significantly. There are several typical reduction strategies available to lower the energy of circuits. By implementing the reduced FA with the leakage power control technique the number of transistors reduced than the normal full adder. The proposed design has static and total power of 5.08nw and 8.33uw for XNOR and for XOR of 12.36nw and 8.56uw. A FA is designed using these technique the obtained results for static and total power are 12.38uw 8.58uw. For the above circuits, a comparison of various static and total power dissipations is conducted. CADENCE-VIRTUOSO is used to simulate circuits using 90nm technology with a 1.2V power supply.

A 42 GHz low phase noise Colpitts VCO in 180-nm SiGe BiCMOS

This paper describes a 39.1 to 42.5 GHz low phase noise Colpitts voltage-controlled oscillator (VCO) using 180-nm SiGe BiCMOS technology. In order to achieve better phase noise, an optimization method related to capacitance ratio is analyzed. Meanwhile, the linearization method is used to achieve a linearized KVCO which is robust to varactor bias variations. The simulated VCO features a tuning range of 8%, low phase noise of –95.3 dBc/Hz at 1 MHz offset, voltage supply of 3.3 V and power consumption of 40 mW, which results in a FOM T of –170 dBc/Hz.

Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors

This paper designs and extends a high speed full adder using 12 MOS Transistors to a ripple carry adder (RCA). The proposed design reduces delay and is effective for Power Delay Product (PDP). Using both complementary MOSFET (CMOS) logic and complementary pass transistor logic(CPL), a new 6T XNOR full adder(FA) is created. CPL is used in the design for Carry and Sum logic in order to minimise circuit delay. The proposed work has a delay of 11.86 ps and a PDP of 0.368fj. By using a newly proposed single bit adder, a 4-bit Ripple Carry Adder(RCA) is designed with 1.2 v supply yielding a power of 572.063uw, delay 0.32ns and PDP 183.06 fj. The outcomes obtained are compared with existing models. For characterstics of speed and PDP, the proposed model outperforms existing models significantly. The circuit was designed in 90nm GPDK technology by using the CADENCE VIRTUOSO TOOL.

A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs

Numerous threats are associated with the globalized integrated circuit (IC) supply chain, such as piracy, reverse engineering, overproduction, and malicious logic insertion. Many obfuscation approaches have been proposed to mitigate these threats by preventing an adversary from fully understanding the IC (or parts of it). The use of reconfigurable elements inside an IC is a known obfuscation technique, either as a coarse grain reconfigurable block (i.e., eFPGA) or as a fine grain element (i.e., FPGA-like look-up tables). This paper presents a security-aware CAD flow that is LUT-based yet still compatible with the standard cell based physical synthesis flow. More precisely, our CAD flow explores the FPGA-ASIC design space and produces heavily obfuscated designs where only small portions of the logic resemble an ASIC. Therefore, we term this specialized solution a “hybrid ASIC” (hASIC). Nevertheless, even for heavily LUT-dominated designs, our proposed decomposition and pin swapping algorithms allow for performance gains that enable performance levels that only ASICs would otherwise achieve. On the security side, we have developed novel template-based attacks and also applied existing attacks, both oracle-free and oracle-based. Our security analysis revealed that the obfuscation rate for an SHA-256 study case should be at least 45% for withstanding traditional attacks and at least 80% for withstanding template-based attacks. When the 80% obfuscated SHA-256 design is physically implemented, it achieves a remarkable frequency of 368MHz in a 65nm commercial technology, whereas its FPGA implementation (in a superior technology) achieves only 77MHz.

An Ultra-Low Power Reconfigurable Biomedical AI Processor With Adaptive Learning for Versatile Wearable Intelligent Health Monitoring.

Wearable intelligent health monitoring devices with on-device biomedical AI processor can be used to detect the abnormity in users' biomedical signals (e.g., ECG arrythmia classification, EEG-based seizure detection). This requires ultra-low power and reconfigurable biomedical AI processor to support battery-supplied wearable devices and versatile intelligent health monitoring applications while achieving high classification accuracy. However, existing designs have issues in meeting one or more of the above requirements. In this work, a reconfigurable biomedical AI processor (named BioAIP) is proposed, mainly featuring: 1) a reconfigurable biomedical AI processing architecture to support versatile biomedical AI processing. 2) an event-driven biomedical AI processing architecture with approximate data compression to reduce the power consumption. 3) an AI-based adaptive-learning architecture to address patient-to-patient variation and improve the classification accuracy. The design has been implemented and fabricated using a 65nm CMOS process technology. It has been demonstrated with three typical biomedical AI applications, including ECG arrythmia classification, EEG-based seizure detection and EMG-based hand gesture recognition. Compared with the state-of-the-art designs optimized for single biomedical AI tasks, the BioAIP achieves the lowest energy per classification among the designs with similar accuracy, while supporting various biomedical AI tasks.

A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications

In this paper, we propose a hybrid crystal oscillator which achieves both quick startup and low steady-state power consumption. At startup, a large negative resistance is realized by configuring a Pierce oscillating circuit with a multi-stage inverter amplifier, resulting in high-speed startup. During steady-state oscillation, the oscillator is reconfigured as a class-C complementary Colpitts circuit for low power consumption and low phase noise. Prototype chips were fabricated in 65nm CMOS process technology. With Pierce-type configuration, the measured startup time and startup energy of the oscillator are reduced to 1/11 and 1/5, respectively, compared with the one without Pierce-type configuration. The power consumption during steady oscillation is 30 μW.

An Energy-Efficient Generic Accuracy Configurable Multiplier Based on Block-Level Voltage Overscaling

Voltage Overscaling (VOS) is one of the well-known techniques to increase the energy efficiency of arithmetic units. Also, it can provide significant lifetime improvements, while still meeting the accuracy requirements of inherently error-resilient applications. This paper proposes a generic accuracy-configurable multiplier that employs the VOS at a coarse-grained level (block-level) to reduce the control logic required for applying VOS and its associated overheads, thus enabling a high degree of trade-off between energy consumption and output quality. The proposed configurable Block-Level VOS-based (BL-VOS) multiplier relies on employing VOS in a multiplier composed of smaller blocks, where applying VOS in different blocks results in structures with various output accuracy levels. To evaluate the proposed concept, we implement 8-bit and 16-bit BL-VOS multipliers with various blocks width in a 15-nm FinFET technology. The results show that the proposed multiplier achieves up to 15% lower energy consumption and up to 21% higher output accuracy compared to the state-of-the-art VOS-based multipliers. Also, the effects of Process Variation (PV) and Bias Temperature Instability (BTI) induced delay on the proposed multiplier are investigated. Finally, the effectiveness of the proposed multiplier is studied for two different image processing applications, in terms of quality and energy efficiency.

3T-SAPON technique to reduce Power Consumption

Scaling down CMOS technology has rapidly improved cost, area effectiveness, switching speed of the circuits & high device reliability. However, scaling has an immense impact on static power consumption in VLSI circuits. For battery operating applications higher power dissipation is not desirable because it reduces the efficiency and cooling effects of the battery. Thus, designing a low-power consuming circuit has become the major criteria in circuit designs. A new circuit model called 3T-SAPON is designed to reduce static power consumption. 3T-SAPON technique power consumption has been reduced around 45%. Using this technique inverter, NAND are implemented and compared with some of the existing standard techniques like LCNT, LECTOR, ONOFIC and SAPON. All these circuits are simulated in Cadence 90nm technology.

Design and Analysis of Four Port Router for Network-On-Chip Applications

System-On-Chip (SoC) is a popular VLSI technology that integrates multiple devices onto a single chip. The Network-On-Chip (NOC) concept, which is a novel paradigm in sophisticated System-On-Chip designs that offers efficient communication throughout the on-chip networks, is used to communicate amongst various devices. The router is the main component in an NoC architecture that is responsible for routing information. Packets are sent through a network by an NoC made up of routers. A routing algorithm divides packets into flow control digits (flits) and determines their paths. The placement of routers is determined by the network topology. In the present work, the main target is to design and analyse the router, which is primarily based on a number of critical factors, including topology, routing algorithm, and packet format. The performance of the suggested router is evaluated and compared to that of the Conventional Wormhole Router (CWHR) with respect to power and slack time (ST). When compared to a traditional wormhole router, the proposed router architecture has 18% less slack. As a result, total power consumption is reduced by 29.3% as compared to traditional wormhole architecture. The architecture is synthesized using Cadence Encounter RTL Compiler using standard 65nm technology.

High Performance VLSI Architecture for DC and Planar Modes of Intra Prediction in HEVC

Abstract: High Efficiency Video Coding (HEVC) achieves improved compression efficiency, but it introduces higher computational complexity due to intricate partitioning and increased angular modes in intra prediction. In this study, we propose a hardware architecture for handling the direct current (DC) and planar modes of intra prediction in the HEVC standard. To evaluate our proposed architecture, we performed synthesis using both TSMC 180nm and TSMC 90nm technologies. We later conducted physical implementation using Physical Cell 90nm technology. The results show significant improvements when moving from TSMC 180nm to TSMC 90nm technology, with the chip area reducing by approximately three times and power consumption decreasing by over six times. After completing the physical layout phase, we obtained a chip area of 112.19 mm2 and a power consumption of 3.88 mW. Comparing the synthesis results with the physical design phase, we observed a slight increase in chip area by around 1.5 times, while the power consumption decreased by approximately 0.4 times. The proposed architecture achieves a throughput of 27 pixels per clock cycle and supports a block size of 16x16, with the potential for further extension

A Machine Learning Based Reliability Analysis of Negative Bias Temperature Instability (NBTI) Compliant Design for Ultra Large Scale Digital Integrated Circuit

NBTI is a key reliability challenge in nanoscale digital design, and it is vital to address it throughout the exploration of design space at high levels of abstraction in order to improve reliability. A prediction model of aging that is adequate for these levels ought to be faster. In addition to this, the model should be able to forecast the recently discovered stochastic consequences of growing older. The purpose of this study is to offer a model that is based on machine learning (ML) and can predict aging effects. After obtaining a training set of sufficient size using Synopsis HSPICE (MOSFET Reliability, MOSRA) in the beginning, the machine-learning-based model is then trained and built in order to forecast the aging statistical features. Evaluation is done on a number of machine learning techniques, including Adaptive Neuro-Fuzzy Inference System (ANFIS), K-Nearest Neighbor (KNN), Support Vector Machine (SVM) and Random Forest (RF). The findings indicate that ANFIS algorithms are very effective in the process of age prediction. The proposed technique shows that the aging prediction runtime is reduced by more than 99% when compared to the MOSRA-based approach, and accurate predictions of the statistical properties of aging are obtained with an accuracy of more than 99% on complementary metal oxide semiconductor (CMOS) and metal gate/high-K (MGK) circuits at the 22nm technology node.

Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures.

Background: This paper presents an efficient two-dimensional (2-D) finite impulse response (FIR) filter using block processing for two different symmetries. Architectures for a general filter (without symmetry) and two symmetrical filters (diagonal and quadrantal symmetry) are implemented. The proposed architectures need fewer multipliers because of the symmetry of the filter coefficients. Methods: A distributed arithmetic (DA)- based multiplication method is used in the proposed architecture. A dual-port memory-based lookup table (DP-MLUT) is used in the multiplication instead of lookup-table (LUT) to reduce the area and power of the FIR filter. The filter's throughput is increased by using block processing. Memory reuse and memory sharing methods are introduced, which reduces the need for many registers and hence the circuit complexity. The architectures are written in Verilog Hardware Description Language and synthesized using Genus Synthesis tool-19.1 in 45nm technology with a generic library of Cadence vendor constraints. The synthesis tool generates the area, delay, and power reports. Power consumption of architectures is calculated with an image size of 64 X 64 and at 20 MHz frequency. Results: Compared to existing architectures, the synthesis results show improvements in power, area, area delay product (ADP), and power delay product (PDP). The proposed MLUT-based 2-D block Quadrantal Symmetry Filter (QSF) for length 8 with block size 4 consumes 58.94% less power, occupies 59.5% less area, 48.44% less ADP and 47.78% less PDP compared to best existing methods. Conclusions: A novel DA-based 2-D block FIR filter architecture with various symmetries is realized. Symmetry is incorporated into the filter coefficients to minimize the number of multipliers. The LUT size is optimized by odd multiples or even multiples storage techniques. Also, the overall area of the architecture is decreased by DP-LUT-based multipliers. The proposed filter architecture is area-power-efficient. It is best suited for applications that have fixed coefficients.

Implementation And Comparison of Different Stages of Current Starved CMOS Ring Oscillator – A Study

The ring oscillators serves as the fundamental building blocks in both digital and analog circuit design, as its extensive use is found in various electrical systems, including phase-locked loops, frequency dividers, and clock generators. This study gives a general overview of the ring oscillator circuit, including its workings, uses, and important design considerations. The ring oscillator generates timing signals for synchronous operation and is often employed as a clock generator in digital systems. It may also be used as a frequency divider to separate higher frequencies into lower ones. A closed loop is used to connect an odd number of inverting stages to create the ring oscillator circuit. An inverter, which is often built using complementary metal-oxide-semiconductor (CMOS) technology, is a component of every stage. By adding a delay to each step, the ring oscillator creates a self-sustaining oscillation. The development and comparison of 3, 5, and 7 stage ring oscillators for different performance metrics, as well as corner analysis for propagation delay and the effect of temperature on the operation of the ring oscillator was performed using Cadence Virtuoso with 90nm technology. This comparison of several phases of a current-starved (CS) ring oscillator offers an advantage to the best design with innovation based on the technology employed and outcomes from the corner analysis, which hasn't been done in any of the more recent researches.

A 1.46–1.96-dB-NF 2.1–5.2-GHz Wideband Passive Balun LNA in 22-nm CMOS

This brief presents a CMOS wideband passive balun low noise amplifier (LNA) based on magnetically coupled resonator (MCR) matching network. The theoretical analysis, expression derivation and simulation verification of the impedance rise with frequency of MCR matching network is presented for the first time. The proposed wideband LNA was fabricated in 22-nm CMOS technology, which achieves a maximum power gain of 15.7 dB, noise figure (NF) of 1.46-1.96 dB. The 3-dB bandwidth ranges from 2.1-5.2 GHz. The minimum power input at 1dB compression point (IP1dB) is -15.2 dBm. The LNA core area is 0.38 mm2 and dissipates a total power of 16 mW from 1 V power supply.

Design of Energy-Efficient RFET-Based Exact and Approximate 4:2 Compressors and Multipliers

The ever-increasing demand for low-power and area-efficient circuits for use in battery-powered devices and the CMOS scaling problems have attracted the attention of VLSI designers to beyond-CMOS technologies like Reconfigurable Field-Effect Transistors (RFETs). Improving the efficiency of multipliers is critical as the core component of many applications such as image processing and Machine Learning (ML). This paper proposes a compact and energy-efficient RFET-based architecture for the 4:2 compressor and Dadda multiplier, leveraging transistor-level reconfigurability and multi-input support of the RFET. Moreover, we propose a novel approximate 4:2 compressor based on efficient RFET logic cells to cater to the needs of error-resilient applications. Extensive circuit-level simulations with 14nm germanium nanowire (GeNW) RFET technology show that the proposed RFET-based exact multiplier improves the power consumption and power-delay product (PDP) by 65% and 45%, respectively, compared to the conventional CMOS-based counterpart in 14nm FinFET technology. Besides, we show that utilizing the proposed approximate compressor, the area and PDP of the multiplier reduce by 46% and 42%. The effectiveness of the approximate multiplier is evaluated in the image multiplication, and the average PSNR and SSIM values are 31.39 and 0.87, respectively.