Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors

Abstract

This paper designs and extends a high speed full adder using 12 MOS Transistors to a ripple carry adder (RCA). The proposed design reduces delay and is effective for Power Delay Product (PDP). Using both complementary MOSFET (CMOS) logic and complementary pass transistor logic(CPL), a new 6T XNOR full adder(FA) is created. CPL is used in the design for Carry and Sum logic in order to minimise circuit delay. The proposed work has a delay of 11.86 ps and a PDP of 0.368fj. By using a newly proposed single bit adder, a 4-bit Ripple Carry Adder(RCA) is designed with 1.2 v supply yielding a power of 572.063uw, delay 0.32ns and PDP 183.06 fj. The outcomes obtained are compared with existing models. For characterstics of speed and PDP, the proposed model outperforms existing models significantly. The circuit was designed in 90nm GPDK technology by using the CADENCE VIRTUOSO TOOL.