Ultra low-power high-speed single-bit hybrid full adder circuit

Abstract

In this paper a low power hybrid 1-bit full adder circuit is designed and extended for 4 bit ripple carry adder (RCA). A new XNOR logic is designed using complimentary-metal-oxide semiconductor (CMOS) logic and Pass transistor logic. CMOS weak inverters improve the power consumption while pass transistors overcome voltage degradation problem. Carry logic is designed using transmission gates which reduces the carry propagation path. A 4-Bit RCA is also designed using the proposed single bit full adder. The proposed full adder and RCA are designed in 180nm technology and post layout simulations are done using Cadence Virtuoso. Power, delay, power delay product (PDP) and area are performance parameters of the proposed full adder which are calculated using umc technology. The power and delay parameters of the proposed single-bit full adder are 930.3-nW and 43.07-ps respectively.