Design and implementation of a Low power Adder Circuit Using LECTOR Technique

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This work implements a 1-bit FA circuit with the CMOS logic with XOR-XNOR combinations. For sum and carry, pass transistors are used to generate the output by combining with XOR, XNOR and CMOS design, and the optimised full adder is implemented with the help of LECTOR technique to control the leakage power. As scaling of CMOS technology has shown improvement in the speed but the leakage power are left to act as major effect. low power VLSI is a new discipline in which high power consumption is becoming an important criteria. But when refers to battery life, high power dissipation is not recommended for device applications. It affects performance, raises cooling expenses, and shortens battery capacity. The switching, dynamic and leakage power changes the inputs significantly. There are several typical reduction strategies available to lower the energy of circuits. By implementing the reduced FA with the leakage power control technique the number of transistors reduced than the normal full adder. The proposed design has static and total power of 5.08nw and 8.33uw for XNOR and for XOR of 12.36nw and 8.56uw. A FA is designed using these technique the obtained results for static and total power are 12.38uw 8.58uw. For the above circuits, a comparison of various static and total power dissipations is conducted. CADENCE-VIRTUOSO is used to simulate circuits using 90nm technology with a 1.2V power supply.