Reducing the Instruction Queue Leakage Power in Superscalar Processors

Abstract

Today's high performance processors operate in the GHz frequency range and dissipate approximately 100 W of power. According to Moore's Law, in the next generation of microprocessors we expect an exponential increase in the total dissipated power. CMOS technology scaling has been the primary factor responsible for the increase in processor performance. A smaller feature size enables designers to increase the clock frequency and transistor count which significantly affects the processor performance. The drawback of such technology scaling is the leakage power dissipation. As the semiconductor technology scales down, the leakage (standby) power also increases exponentially and accounts for an increasing share of a processor's total power dissipation. This issue becomes a serious problem in mobile hardware where applications may generate long periods of inactivity. In this paper we take a step towards reducing the leakage power dissipation of the instruction queue which allows the out of order execution in a superscalar processor. This unit is responsible for up to 27% of total chip power dissipation in typical superscalar microprocessors. In particular, we reduce the leakage power in the thousands of comparator units in the instruction queue by applying a power gating technique. We rely on detecting the idle time in all comparators. We show that the comparators in the instruction queue stay idle for typically 50% of the total program execution time. This figure is based on the observation that the whole processor pipeline approaches an idle state when a combination of instruction and data cache misses occur. When such idle time is detected we apply power gating to turn off all the comparator units thereby eliminating the leakage power. Our results show that by power gating the comparators using our idle time detecting algorithm it is possible to reduce their leakage power dissipation by up to 95%