Abstract
Scaling down CMOS technology has rapidly improved cost, area effectiveness, switching speed of the circuits & high device reliability. However, scaling has an immense impact on static power consumption in VLSI circuits. For battery operating applications higher power dissipation is not desirable because it reduces the efficiency and cooling effects of the battery. Thus, designing a low-power consuming circuit has become the major criteria in circuit designs. A new circuit model called 3T-SAPON is designed to reduce static power consumption. 3T-SAPON technique power consumption has been reduced around 45%. Using this technique inverter, NAND are implemented and compared with some of the existing standard techniques like LCNT, LECTOR, ONOFIC and SAPON. All these circuits are simulated in Cadence 90nm technology.
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