6T Static Random Access Memory Cell Research Articles

CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adopted semi-parallel architecture efficiently stores filters from multiple CNN layers by sharing eight standard 6T SRAM cells with one charge-domain MAC circuit. Moreover, up to six levels of bit-width of weights with two encoding schemes and eight levels of input activations are supported. A 7-bit charge-injection SAR (ciSAR) analog-to-digital converter (ADC) getting rid of sample and hold (S&H) and input/reference buffers further improves the overall energy efficiency and throughput. A 65-nm prototype validates the excellent linearity and computing accuracy of CAP-RAM. A single 512x128 macro stores a complete pruned and quantized CNN model to achieve 98.8% inference accuracy on the MNIST data set and 89.0% on the CIFAR-10 data set, with a 573.4-giga operations per second (GOPS) peak throughput and a 49.4-tera operations per second (TOPS)/W energy efficiency.

Low Power PPN inverter based 10T SRAM Cell

Objectives: In the present power-hungry world, the objective of this paper is to design a system that helps in the reduction of power consumption of systems. A memory cell, more specifically an SRAM cell being the major contributor to the increased power becomes an important unit to be considered in such systems for reducing power. This paper presents an improved single-ended PPN inverter based 10T SRAM cell. Methods: The proposed cell makes use of PPN-inverters. The CMOS inverter is replaced by the PPN-inverter in the conventional 8T SRAM cell giving an improved single-ended PPN-based 10T SRAM cell. Findings: The proposed work is compared with other SRAM cells based on delay, power dissipation, and power delay product (PDP). The proposed cell is designed and simulated on Cadence Virtuoso EDA tool version IC6.1.7 at a standard CMOS 45nm technology. The simulation results show that the proposed SRAM cell consumes lesser power and hence lower PDP compared to conventional 8T SRAM cell as well as other SRAM cells and with the use of high threshold voltage transistors in the read circuit a further decrease in the power consumption is observed. So, by use of PPN inverter in 8T SRAM cell a new design for low power consuming SRAM cell is achieved. Novelty: The proposed cell is optimized in terms of power dissipation making it more efficient for use in portable battery-operated devices. Keywords 10T SRAM cell, Low power, PPN inverter, Static Random­Access Memory (SRAM)

A 4 × 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications

In ultra-low-power applications, the design of power-efficient static random access memory (SRAM) is a major concern as it plays a significant part in leakage due to its higher density. In this paper, we have designed a power-efficient SRAM array that efficiently utilizes our SRAM cell for low-power and reliable memory applications. The proposed SRAM array is designed with an optimized 8T SRAM cell with minimum leakage and improved stability. The cell designed with 22 nm CMOS technology uses a stacking effect to further enhance leakage reduction and transmission gate as an access transistor to obtain better stability. Peripheral circuitry like address decoder, write driver, pre-charge, and sense amplifier are designed with optimum transistor sizing to get superior results in terms of area occupied and power consumption. The read and write access time for the cell is found to be 12 ps and 10 ps respectively. In line with the 22 nm technology node, the power is calculated for the array as 0.42 µW.

Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region

The major design parameters of embedded cache memory (SRAM memory cell) are speed, power consumption, noise tolerance, and reliability. It is a challenging task to design an SRAM cell in the face of process, voltage, and temperature variations at low supply voltages. At scaled technology node the conventional 6T SRAM cell suffers from read and write failures as well as instability. Moreover, it is susceptible to multibit soft error rate since it does not support bit-interleaving architecture. This paper proposes a low-power robust single bitline 9T (nine transistor) SRAM (Static Random Access Memory) at a 16-nm technology node in the subthreshold region. The potency of the proposed cell is shown by comparing it with other recently published SRAM cells, namely, single-ended NTV 9T (SENTV9T), write and read enhanced 9T (WREN9T), and the conventional 6T (CONV6T) SRAM cells. The proposed cell provides 1.25×/1.96 × lower read current IREAD variability compared with WREN9T/SENTV9T. The proposed cell achieves 4.23 × higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with CONV6T due to the fact that it employs read decoupled operation. Moreover, SBL9T consumes lower standby power during hold state and dynamic power in the active state as compared with SENTV9T, WREN9T, and CONV6T. SBL9T also exhibits 10.01×/8.65×/11.47× narrower spread in standby power compared with CONV6T/WREN9T/SENTV9T. The dynamic power spread shows a similar trend with SBL9T providing 1.97×/1.02× narrower spread in dynamic power compared with WREN9T/SENTV9T. These benefits however are achieved by the SBL9T at the cost of 1.28×/0.71×/1.01× longer read delay compared with CONV6T/WREN9T/SENTV9T.

Investigation of 7T SRAM Cell for IoT based devices

Internet of Thing (IoT) based devices require the design of ultra-low power Static Random Access Memory (SRAM) to sustain the long battery life. In present work, for execution different types of SRAM cell methodologies Cadence Virtuoso tool is used and all considered methodologies read and write operations have been supervised out. These SRAM cell methodologies various parameters also have been calculated, there are read static noise margin (RSNM), write static noise margin (WSNM), read delay, write delay, read power and write power. For low read, write power dissemination and faster read and write working new 7T SRAM cell methodology is proposed. It has been recognized that new 7T SRAM cell methodology as collated to 6T to 9T SRAM cell methodologies read power consumption reduced by 1.60* to 4*. New 7T SRAM cell methodology as collated to traditional 6T, 8T and 9T SRAM cell write power consumption is decreased by 2.3* to 2.6*. It is also noticed that as collated to 6T, 8T and 9T SRAM cell methodology that new 7T SRAM read delay suppressed by 2.40* to 2.60* and its write delay is also suppressed by 3.80* to 99*. As collate to 6T to 9T SRAM cell methodologies write operation robustness of new 7T SRAM cell is 3.0* to 6.5* perform in better way. New 7T SRAM cell has the tradeoff that its read operation robustness is 6* to 14* lesser as collate to 6T, 8T and 9T SRAM cell methodologies. Due to low power consumption and less delay new 7T SRAM cell methodology is suitable for Internet of things (IOT) based devices.

Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability

The technology is shrinking in recent days which leads to growing concerns related to various design metrics. Leakage power tends to grow with the array size as most of the Static Random Access Memory (SRAM) cells operate in standby mode. The data to be written into the SRAM become difficult as the supply voltage decreases. So, stability in write mode requires enhancement. As SRAM is used for the on-chip computations, the faster write operation is required. The half-select issue in SRAM design needs to be eliminated so that bit interleaving architecture can be employed for the SRAM array enabling the protection from soft errors. A new Proposed 10 Transistor Bit-Interleaved SRAM cell has been designed addressing the above concerns. Employment of high-threshold voltage devices in read path and absence of NMOS device in one of the inverters reduces leakage power. Cut-off switch enables faster write operation and enhanced write stability. Cross point selection in write mode eliminates the half-select issue observed by carrying 1000 Monte-Carlo simulations. It has lower leakage power while holding 0 compared to 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at the worst fast-fast process corner for 0.9 V supply voltage. Write 1 Power Delay Product is lower than 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at slow-slow corner at 0.9V supply voltage. All the design metrics have been evaluated by performing post-layout simulation in Cadence Virtuoso in 45-nm technology.

Design and Implementation of Low Power High Stability 8T SRAM

This paper examines about the power decrease system in a memory cell. It affords a low power high stability 8T Static Random Access Memory (SRAM) cell. Two typically used SRAM cells are analyzed in phrases of their stability and power. It presents improved performance as analyzed with traditional 6T SRAM cell in iterms iof leakage power and static noise margin. The scheme of low power 8T SRAM is executed along enforcing power gating approach. Power gating is executed with the aid of putting a transistor in between the 8T SRAM cell and VDD or ground. However, this avoids the direct VDD and ground path and forming an indirect VDD and indirect ground path. The static noise margin of 8T SRAM is computed to decide higher stability whilst compared with 6T SRAM. It is inferred that the power of the newly programmed 8T SRAM cell is diminished close to 1.5% as contrasted with that of the traditional 8T SRAM cell and the stability is improved close to 8.19%.

Design and Analysis of SRAM cell using Body Bias Controller for Low Power Applications

Low power consumption of electronic devices has become one of the most desirable factors in the present day’s technology. Static random access memory (SRAM) being an integral part of most of the electronic gadget suffers from leakage current which results in static power dissipation and subsequently affects its performance particularly during standby or hold mode. This becomes crucial especially for those systems which are portable and have limited power supply. This work therefore proposes a body bias controller implemented with a 7T SRAM cell at 28 nm CMOS technology node which lowers the static power consumption and increases the hold static noise margin (HSNM) of SRAM during standby mode by changing the threshold voltage. Moreover, it also reduces write delay due to reduction in threshold voltage of proposed design without having a significant effect on write static noise margin and read static noise margin. It has been noticed that there is a reduction of 40%, 28%, 41.9% and 30% in static power dissipation whereas there is an enhancement of 19%, 14.2%, 6.6% and 5.2% in HSNM of the proposed design when compared to 6T SRAM cell, 7T SRAM cell, WRE8T SRAM cell and 9T SRAM cell, respectively. The proposed design can thus be a suitable alternative for low power SRAMs.

A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era

The growing demand of Internet of things based portable gadgets motivate to develop low power static random access memory (SRAM) cell. It occupies large portion in modern system on chip devices. In this context, a detailed review on various SRAM cell topologies has been performed which includes comparative analysis of design parameters and challenges. To perform the comparative analysis, considered SRAM cell topologies are simulated with cadence virtuoso IC6.1.5-64b at 45 nm generic process design kit technology file. It is worthy to notice that 9T SRAM cell has highest value of read stability among considered cells. It is attributed to use of differential read decoupled structure. The 7T SRAM cell has highest value of write ability among considered cells. It is observed that 8T SRAM cell has lowest read power dissipation among considered cells. It happens due to the use of stack transistor in read path of the cell. The lowest value of read access time is also observed in 8T SRAM cell among considered SRAM cells. It is 1.82 $$\times$$ higher as compared to conventional 6T SRAM cell. Further, the write access time of 9T SRAM cell is lowest among considered cells. This is 1.41 $$\times$$ less as compared to conventional 6T SRAM cell. Static noise per unit area to power delay product ratio (SAPR) is used to evaluate the overall performance of considered SRAM topologies. It is observed that 8T SRAM cell has the highest value of SAPR among considered SRAM cells. It is 1.91 $$\times$$ as compared to conventional 6T SRAM cell. All the comparison has been done at 1.0 V supply voltage.

A Schmitt-trigger based low read power 12T SRAM cell

In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52 $$\times$$ and 1.86 $$\times$$ lesser variability in read current and read power respectively as compared to conventional 6T SRAM cell. Further, the write access time/read access time of the proposed topology are improved by $$1.71 \times /1.82 \times$$ as compared to 6T SRAM cell. The read power delay product of proposed ST12T cell is minimum with variation in supply voltage from 0.5 to 1 V when compared with all considered SRAM cells. ST12T SRAM cell also exhibits 26.82% and 8.87% higher read static noise margin and write static noise margin respectively as compared to conventional 6T SRAM cell. This may be attributed to Schmitt trigger design of inverters in core latch of proposed SRAM cell. The proposed bit-cell is free from half select issue and supports bit interleaving format. Authors have used cadence virtuoso tool with Generic Process Design Kit 45 nm technology file to carry out simulation.

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell

This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by [Formula: see text] as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than the considered D2p11T cell. The proposed 10T cell shows [Formula: see text] and [Formula: see text] narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by [Formula: see text] as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are [Formula: see text] and [Formula: see text] lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45[Formula: see text]nm technology file has been utilized to carry out simulations.

A low-power small-area 6T SRAM cell for tracking detector applications

This paper presents a novel six-transistor (6T) Static Random Access Memory (SRAM) cell, which uses only one bit line and applies an additional switch to cut the competition path during the write access. The proposed 6T SRAM cell has been applied in a pixel array detector to configure a digital-to-analog converter in each pixel to improve the charge threshold uniformity. Compared to the conventional 6T SRAM cell, the proposed 6T SRAM cell features lower power consumption and smaller area. Simulation results show the power consumption is reduced by about 43% and all the transistors are designed by minimum size to reduce the area but without the performance degradation. The test results show that the novel 6T SRAM cell works very well.

Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

Single bit‐line 11T SRAM cell for low power and improved stability

This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation. The proposed cell has a separate read and write path which successfully improves read and write abilities. Furthermore, it solves the row half select disturbance and utilises a row-based virtual ground signal to eliminate unnecessary bit-line discharge in the un-selected row, thus decreasing energy consumption. The cell also achieves low power due to the stack effect. To show the effectiveness of the cell, its design metrics are compared with other published SRAM cells, namely, conventional 6T, 10T, 9T, and power-gated 9T (PG9T). In standby mode, from 6.71 to 7.37% leakage power reduction is observed for this cell at an operating voltage of 1.2 V and 29.21 to 58.68% & 32.74 to 71.11% improvement for write & read power over other cells. The proposed cell exhibits higher write and reads static noise margins with an improvement of 13.54 and 63.28%, respectively, compared to conventional 6T SRAM cell. The cell provides write delay improvement from 29.77 to 49.40% and read delay improvement from 7 to 12% compared to 9T, 10T, and PG9T, respectively.

Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond

This article presents a comprehensive assessment on the 6T static random access memory (SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device-circuit cooptimization. Seven key device design parameters and their multiple impacts on a 6T SRAM cell are systematically evaluated, focusing on materials band engineering, device design, circuit parameters tradeoff, and variation control. The area of SRAM cell under the same Fin quantization scheme remains constant in all evaluations. To the best of our knowledge, the most comprehensive discussion about circuit optimization from multiple device design parameters perspective is presented. Based on our cooptimization scheme, a SRAM cell is effectively designed. For a low-power and robust SRAM cell design, we achieve 56.7% reduction in leakage, 7.9% improvement in hold noise margin (HNM), 8.6% improvement in read noise margin (RNM), and 10.8% improvement in write margin (WM) at the expense of 19.3% increase in delay under design space of gate length (Lg) and spacer thickness (TSPC). For a high-speed SRAM cell design, we recommend focusing on the optimization of architecture and peripheral circuits. This framework not only has the advantages of easy implementation, technology-friendly, and high accuracy, but also suitable for path-finding researches on 5-nm node and beyond.

Design of a Stable Low Power 11-T Static Random Access Memory Cell

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by [Formula: see text] and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.

Characterization of various FinFET based 6T SRAM cell configurations in light of radiation effect

The microelectronics circuits used in the aerospace applications work in an extremely radiated environment, causing a large possibility of a single event upset (SEU). Static random access memory (SRAM) is the most susceptible of these circuits as it occupies a significant area of the recent System-on-Chip (SoC) and also frequently store important data. Therefore, retaining data integrity with regards to SEUs has become a primary requirement of SRAM bit-cell design. Use of FinFET devices in the SRAM cell can offer higher resistance against radiation compared to the CMOS counterparts. In this work, using TCAD simulations, we have analysed effect of SEU on three different FinFET based 6T bit-cell configurations, in which number of fins in the access and pull-down transistors are different. We have analysed the effect of SEU at an angle of 90° and 60°.

High Stable and Low Power 10T CNTFET SRAM Cell

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

Hybrid on-chip soft computing model for performance evaluation of 6T SRAM cell using 45-nm technology

A hybrid on-chip approach based on the variants of soft computing techniques is proposed in this work to evaluate the performance metrics of a 6T static random access memory (SRAM) cell in 45-nm technology. The performance metric evaluated for the SRAM cell is the data retention voltage (DRV) with optimal memory requirements. Each of the SRAM memory cells intends the chip to possess low density but operates at high speed. This paper formulates a hybrid soft computing framework comprising a deep backpropagation neural network which trains the fuzzy inference system to determine the performance metrics of 6T SRAM cell. The weight and bias parameters of the deep learning neural framework are optimized through a cat swarm optimization algorithm so as to reduce the elapsed convergence time of the new hybrid soft computing model. Evaluation process is executed based on the driven outputs from deep learning model to the fuzzy inference system (FIS) module so as to achieve the best values of DRV. Data retention voltage plays a major role in reducing the substantial leakage current and static noise margin intends to retain the data without losing them. Deep backpropagation neural network gets trained with deep learning procedures and optimizes the rule parameters and membership parameters of the FIS design structure. The performance metric DRV under various constraints prove to be better and effective in comparison with the solutions from the existing literature works for the same configuration of 6T SRAM cell using 45-nm technology.

Characterization of Half-Select Free Write Assist 9T SRAM Cell

Modern biomedical applications have created a high demand for low power static random access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T (HFWA9T) cell has been proposed. To analyze the impact of process variations on different design metrics, the proposed cell has been compared with other contemporary designs such as feedback-cutting 7T (7T), fully differential 8T (FD8T), and single-ended disturb free 9T (SEDF9T) cells. The HFWA9T cell exhibits 2.87×/3.37× higher read stability or read static noise margin (RSNM) than that of 7T/FD8T and 1.40×/6.55× higher write ability or write static noise margin (WSNM) than that of FD8T/SEDF9T,2.90×/2.67× and 1.06×/1.01×/5.05× narrower spread in RSNM and WSNM than that of 7T/FD8T and 7T/FD8T/ SEDF9T cells, respectively. In addition, it shows 1.11×/1.03× narrower spread in read delay (TRA) than that of FD8T/SEDF9T and 1.33× shorter TRA than that of SEDF9T cell. Furthermore, it consumes only 0.67×/0.31×/0.48× of the write power and 0.262×/0.605×/0.90× of the read power, respectively, consumed by 7T/FD8T/SEDF9T, while consuming 0.34×/0.96× of static power consumed by 7T/FD8T cell. For all these improvements, it incurs a penalty of 1.62×/1.78× in write delay (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WA</sub> ) compared to 7T/SEDF9T and 1.58×/1.58× in T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RA</sub> compared to 7T/FD8T cell at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 700 mV.