A low-power small-area 6T SRAM cell for tracking detector applications

Abstract

This paper presents a novel six-transistor (6T) Static Random Access Memory (SRAM) cell, which uses only one bit line and applies an additional switch to cut the competition path during the write access. The proposed 6T SRAM cell has been applied in a pixel array detector to configure a digital-to-analog converter in each pixel to improve the charge threshold uniformity. Compared to the conventional 6T SRAM cell, the proposed 6T SRAM cell features lower power consumption and smaller area. Simulation results show the power consumption is reduced by about 43% and all the transistors are designed by minimum size to reduce the area but without the performance degradation. The test results show that the novel 6T SRAM cell works very well.