Characterization of various FinFET based 6T SRAM cell configurations in light of radiation effect

Abstract

The microelectronics circuits used in the aerospace applications work in an extremely radiated environment, causing a large possibility of a single event upset (SEU). Static random access memory (SRAM) is the most susceptible of these circuits as it occupies a significant area of the recent System-on-Chip (SoC) and also frequently store important data. Therefore, retaining data integrity with regards to SEUs has become a primary requirement of SRAM bit-cell design. Use of FinFET devices in the SRAM cell can offer higher resistance against radiation compared to the CMOS counterparts. In this work, using TCAD simulations, we have analysed effect of SEU on three different FinFET based 6T bit-cell configurations, in which number of fins in the access and pull-down transistors are different. We have analysed the effect of SEU at an angle of 90° and 60°.