4H-SiC Epitaxial Wafers Research Articles

Influence of Growth Process on Suppression of Surface Morphological Defects in 4H-SiC Homoepitaxial Layers.

To address surface morphological defects that have a destructive effect on the epitaxial wafer from the aspect of 4H-SiC epitaxial growth, this study thoroughly examined many key factors that affect the density of defects in 4H-SiC epitaxial wafer, including the ratio of carbon to silicon, growth time, application of a buffer layer, hydrogen etching and other process parameters. Through systematic experimental verification and data analysis, it was verified that when the carbon-silicon ratio was accurately controlled at 0.72, the density of defects in the epitaxial wafer was the lowest, and its surface flatness showed the best state. In addition, it was found that the growth of the buffer layer under specific conditions could effectively reduce defects, especially surface morphology defects. This provides a new idea and method for improving the surface quality of epitaxial wafers. At the same time, we also studied the influence of hydrogen etching on the quality of epitaxial wafers. The experimental results show that proper hydrogen etching can optimize surface quality, but excessive etching may lead to the exposure of substrate defects. Therefore, it is necessary to carefully control the conditions of hydrogen etching in practical applications to avoid adverse effects. These findings have important guiding significance for optimizing the quality of epitaxial wafers.

Multiple-Layer Triangular Defects in 4H-SiC Homoepitaxial Films Grown by Chemical Vapor Deposition

In this study, a special triangular defect (TD) was identified on 4H-SiC epitaxial wafers. The morphology and composition characteristics of these special TDs were revealed by Raman, atomic force microscope (AFM), and scanning electron microscope (SEM). Compared to ordinary triangular defects, this defect protruded from the epitaxial layer and exhibited a laminated shape. The study also discussed the effects of several factors, such as C/Si ratio and growth time, on the triangular defects. Through analysis of these results, we developed methods to suppress the triangular defects. This research provides new insights into the morphology, structure, and composition of this serious destructive defect and is helpful for improving the performance of SiC epitaxial wafers.

PL Signatures from Decoration of Dislocations in SiC Substrates and Epitaxial Wafers

Photoluminescence (PL) signatures of 4H-SiC bare and epitaxial wafers from a surface inspection tool have been studied. Large variations in PL black or white dot densities were confirmed for comparable crystal quality and growth process conditions. Comparison with KOH etching results confirms that both PL black and white dots are tied to discrete threading dislocations. PL spectra results suggest dislocation decoration by donor-acceptor pairs.

Study and reduction of the surface pits in 4H-SiC epitaxial wafer

Pit defects in SiC epitaxial materials is a new issue which shows an influence on different type of SiC devices such as SBD and MOS. The surface pits generated a leakage current and caused the occurrence of a local electric field crowding in the SBD. While the original and mechanism of the surface pits is still not clear. In the paper, the original and reduction of surface pits during 4H-SiC homoepitaxial growth by a warm wall planetary reactor have been investigated. The C/Si ratio and Cl/Si ratio have great effects on the surface pits. Lower C/Si ratio and higher Cl/Si ratio will form a Si-rich environment on the wafer surface during growth, which is crucial for reduction of the surface pits in 4H-SiC epitaxial wafer. With the optimized parameters, high quality epi-wafer with lower pit defects density has been obtained.

High-Temperature Performance of the 4H-SiC n-p-n Bipolar UV Phototransistor

Excellent high-temperature performance (298–523 K) of the 4H-SiC n-p-n bipolar phototransistor detector (PTD) was explored. It was fabricated using the 4H-SiC epitaxial wafer grown by high-temperature chemical vapor deposition (HTCVD). The static and dynamic properties of the device were tested and analyzed. The results show that the device still has an optical gain of up to 103, a wide linear response range, and good repeatability at the high temperatures up to 523 K under a 3-V bias with a wavelength of 360 nm. The temperature coefficient of the optical gain is extracted, the value of which is 1.02/K. Although the response time of the device increases with the temperature, the increased percentage in responsivity is significantly greater than that of the response time. The results provide an important experimental reference for the application of high-temperature detection and suggest that the PTD has the potential to be used in ultraviolet (UV) detecting systems at high temperatures.

Suppression of stacking-fault expansion in 4H-SiC PiN diodes using proton implantation to solve bipolar degradation

4H-SiC has been commercialized as a material for power semiconductor devices. However, the long-term reliability of 4H-SiC devices is a barrier to their widespread application, and the most important reliability issue in 4H-SiC devices is bipolar degradation. This degradation is caused by the expansion of single Shockley stacking-faults (1SSFs) from basal plane dislocations in the 4H-SiC crystal. Here, we present a method for suppressing the 1SSF expansion by proton implantation on a 4H-SiC epitaxial wafer. PiN diodes fabricated on a proton-implanted wafer show current–voltage characteristics similar to those of PiN diodes without proton implantation. In contrast, the expansion of 1SSFs is effectively suppressed in PiN diodes with proton implantation. Therefore, proton implantation into 4H-SiC epitaxial wafers is an effective method for suppressing bipolar degradation in 4H-SiC power-semiconductor devices while maintaining device performance. This result contributes to the development of highly reliable 4H-SiC devices.

Thermal-annealing behavior of in-core neutron-irradiated epitaxial 4H[sbnd]SiC

The effect of thermal annealing on defect recovery of in-core neutron-irradiated 4HSiC was investigated. Au/SiC Schottky diodes were manufactured using a 4HSiC epitaxial wafer that was neutron-irradiated at the HANARO research reactor. The electrical characteristics of their epitaxial layers were analyzed under various conditions, including different neutron fluences (1.3 × 1017 and 2.7 × 1017 neutrons/cm2) and annealing times (up to 2 h at 1700 °C). Capacity–voltage measurements showed high carrier compensation in the neutron-irradiated samples and a recovery tendency that increased with annealing time. The carrier density could be recovered up to 77% of the bare sample. Deep-level-transient spectroscopy revealed intrinsic defects of 4HSiC with energy levels 0.47 and 0.68 eV below the conduction-band edge, which were significantly increased by in-core neutron irradiation. A previously unknown defect with a high electron-capture cross-section was discovered at 0.36 eV below the conduction-band edge. All defect concentrations decreased with 1700 °C annealing; the decrease was faster when the defect level was shallow.

Surface flattening of 4H-SiC (0001) epitaxial wafers by high temperature oxidation

Due to the special ‘step-controlled epitaxy’ mode of 4H-SiC, it is easy to generate step bunching on the surface. Although the flatness of epitaxial wafers has been greatly improved with the advancement of epitaxy technology, there are still localized steps on the surface of some certain wafers. The presence of localized steps can affect the performance of the subsequently fabricated devices. Therefore, minimizing or even eliminating the local steps of the epitaxial surface to obtain an atomically smooth surface is very important. Here, we utilize a high-temperature oxidation process to reduce the size of the giant steps and obtain a flatter epitaxial surface. We found that oxidation parameters such as temperature, pressure, and time play an important role in the surface planarization, and the degree of planarization can be further improved by multiple oxidation processes. In addition, although the oxidation rate under low pressure is lower than that under atmospheric pressure, a smoother epitaxial surface can be obtained. Our results demonstrate the possibility of obtaining atomically smooth surfaces through a high-temperature oxidation process.

Impacts of hydrogen annealing on the carrier lifetimes in p-type 4H-SiC after thermal oxidation

Thermal oxidation and hydrogen annealing were applied on a 100 μm thick Al-doped p-type 4H-SiC epitaxial wafer to modulate the minority carrier lifetime, which was investigated by microwave photoconductive decay (μ-PCD). The minority carrier lifetime decreased after each thermal oxidation. On the contrary, with the hydrogen annealing time increasing to 3 hours, the minority carrier lifetime increased from 1.1 μs (as-grown) to 3.14 μs and then saturated after the annealing time reached 4 hours. The increase of surface roughness from 0.236 nm to 0.316 nm may also be one of the reasons for limiting the further improvement of the minority carrier lifetimes. Moreover, the whole wafer mappings of minority carrier lifetimes before and after hydrogen annealing were measured and discussed. The average minority carrier lifetime was up to 1.94 μs and non-uniformity of carrier lifetime reached 38% after 4-hour hydrogen annealing. The increasing minority carrier lifetimes could be attributed to the double mechanisms of excess carbon atoms diffusion caused by selective etching of Si atoms and passivation of deep-level defects by hydrogen atoms.

Evaluation of Line-Shape Defect in Epitaxial Wafer

In this study, we investigated the origin of line-shape defect in 4H-SiC epitaxial wafers. The inspection results revealed that such defects resulted from the substrate entirely and accompanied with dislocation lines during the epitaxial process. Although the defect surface condition with nanometer level of roughness seemed to do little harm to the initial electrical characteristics of power devices, dislocation lines possibly resulted in high leakage current when reverse voltage was applied. To reduce line-shape defects, it is essential to reduce defects and threading dislocations in substrates and to develop a nondestructive method for wafer screening.

Effects of stress on the evolution of Σ-shaped dislocation arrays in a 4H-SiC epitaxial layer

Five Σ-shaped dislocation arrays in 100-mm-diameter, 12-μm-thick 4H-SiC epitaxial wafers were observed using photoluminescence mapping. The structure of the Σ-shaped dislocation arrays was characterized using nondestructive analytical techniques of photoluminescence mapping, microphotoluminescence spectroscopy, and x-ray topography. Each Σ-shaped dislocation array consists of two basal plane dislocations (BPDs) at the interfacial dislocation terminal points and two half-loop arrays. The interfacial dislocation pairs nucleate from BPDs in the substrate. Three independent stresses lead to interfacial dislocations: thermal stress (τT), stress induced by misfit strain (τM), and interaction force (τI). The main cause of interfacial dislocation formation is attributed to the development of τT within the wafer due to temperature nonuniformity. τM and τI also contribute to the formation of interfacial dislocations. Larger stresses increase the BPD glide velocity in the interfacial dislocations, thereby producing longer Σ-shaped dislocation arrays.

Defect characterization and charge transport measurements in high-resolution Ni/n-4H-SiC Schottky barrier radiation detectors fabricated on 250 μm epitaxial layers

Advances in the growth processes of 4H-SiC epitaxial layers have led to the continued expansion of epilayer thickness, allowing for the detection of more penetrative radioactive particles. We report the fabrication and characterization of high-resolution Schottky barrier radiation detectors on 250 μm thick n-type 4H-SiC epitaxial layers, the highest reported thickness to date. Several 8 × 8 mm2 detectors were fabricated from a diced 100 mm diameter 4H-SiC epitaxial wafer grown on a conductive 4H-SiC substrate with a mean micropipe density of 0.11 cm−2. From the Mott–Schottky plots, the effective doping concentration was found to be in the range (0.95–1.85) × 1014 cm−3, implying that full depletion could be achieved at ∼5.7 kV (0.5 MV/cm at the interface). The current-voltage characteristics demonstrated consistently low leakage current densities of 1–3 nA/cm2 at a reverse bias of −800 V. This resulted in the pulse-height spectra generated using a 241Am alpha source (5486 keV) manifesting an energy resolution of less than 0.5% full width at half maximum (FWHM) for all the detectors at −200 V. The charge collection efficiencies (CCEs) were measured to be 98–99% with no discernable correlation to the energy resolution. A drift-diffusion model fit to the variation of CCE as a function of bias voltage, revealed a minority carrier diffusion length of ∼10 μm. Deep level transient spectroscopy measurements on the best resolution detector revealed that the excellent performance was the result of having ultralow concentrations of the order of 1011 cm−3 lifetime limiting defects—Z1/2 and EH6/7.

Low-Voltage and High-Gain Ultraviolet Detector Based on 4H-SiC n-p-n Bipolar Phototransistor

A two-terminal 4H-SiC n-p-n bipolar phototransistor detector (PTD) with high gain is demonstrated. It was fabricated using the 4H-SiC epitaxial wafer grown by high-temperature chemical vapor deposition. The PTD shows a large photocurrent and responsivity enhancement over the conventional 4H-SiC p-i-n photodetector (PD). These enhancement effects are owing to the internal gain of the bipolar transistor. The detector shows a high optical gain of ~ 1450 at 360 nm and has a linear response to the ultraviolet (UV) light in the wide light intensity range of 0.7– $700~\boldsymbol \mu \text{W}\boldsymbol /$ cm2 at a low operating voltage of 3 V. The PTD can respond to the UV light from 220 to 340 nm and the peak responsivity is $\sim 125~\text{A}\boldsymbol /\text{W}$ at 275 nm. This work is significant for developing high-performance SiC-based bipolar phototransistors.

Influence of surface relaxation on the contrast of threading edge dislocations in synchrotron X-ray topographs under the condition of g · b = 0 and g · b × l = 0

Residual contrast of threading edge dislocations is observed in synchrotron back-reflection X-ray topographs of 4H-SiC epitaxial wafers recorded using basal plane reflections where both g · b = 0 and g · b × l = 0. The ray-tracing simulation method based on the orientation contrast formation mechanism is applied to simulate images of such dislocations by applying surface relaxation effects. The simulated contrast features match the observed features on X-ray topographs, clearly demonstrating that the contrast is dominated by surface relaxation. Depth profiling indicates that the surface relaxation primarily takes place within a depth of 5 µm below the surface.

The Influence of Tri-Defects of Epitaxial Layers on the Performance of 4H-Sic Diodes

The triangular defect is a common defect in the 4H-SiC epitaxy, which is also one of the killer defects to the 4H-SiC devices. In this paper, the 4H-SiC epitaxial wafer was grown by chemical vapor deposition (CVD). The formation mechanism of triangular defects in silicon carbide epitaxy was analyzed, and the solutions were proposed. Then, the diodes were fabricated on the wafer, and the influence of triangular defects on the forward and reverse I-V characteristics of 4H-SiC diodes was analyzed by tracking the defects map. The results show that the presence of triangular defects can lead to the reduction of the reverse voltage by about 40%, an increase of the leakage current by four orders of magnitude, and an increase of the forward conduction resistance.

Understanding the breakdown asymmetry of 4H-SiC power diodes with extended defects at locations along step-flow direction

Power electronic devices for high-voltage applications prefer wide-bandgap semiconductors such as silicon carbide, whereas the immaturity of epitaxial growth technology introduces many extended defects, some of which are crucial to the electrical performance of fabricated devices. Therefore, it is much expected to find out some deep relation between extended defects and device performance. In this work, based on comparisons of breakdown behaviors of 4H-SiC power diodes with or without extended defects of different types, the importance of several features of the extended defect, including the distance, length, and orientation, is reported. Besides, based on the experimental results from dark-field microscopy, near-ultra-violet photoluminescence and topography, and theoretical analysis with numerical calculations, the mechanism of a particular asymmetric breakdown behavior in 4H-SiC devices along the step-flow direction is revealed, which originates from the prevalent step-controlled epitaxy technology for the commercial 4H-SiC epitaxial wafer. With the proposed result and understanding, it is possible to achieve a higher yield in production at a similar material cost.

Characterization and Reduction of Defects in 4H-SiC Substrate and Homo-Epitaxial Wafer

4H-SiC substrates and homo-epitaxial layers were obtained using the traditional methods of physical vapor transport and chemical vapor deposition. Defect morphology has been studied using both Synchrotron White Beam X-ray Topography and Monochromatic Beam X-ray Topography. Molten KOH etching method was adopted to further investigate the dislocation behavior mechanisms. Deflected dislocations were observed at the periphery regions in both substrate and epitaxial wafers. 3C polytypes and half loop arrays were observed in the 4H-SiC epitaxial wafer. It is also found that the majority of basal plane dislocations are converted to threading edge dislocations in the epitaxial wafer samples. The proportion of BPD to TED conversion depends on the surface step morphology and growth mode in epitaxial growth which in turn depends on the C/Si ratio. By the optimization of etching time prior to epitaxy and C/Si ratio, high-quality epitaxial wafers with extremely low basal plane dislocations densities (＜0.1 cm-2) was obtained.

Review and Detail Classification of Stacking Faults in 4H-SiC Epitaxial Layer by Mirror Projection Electron Microscopy

Stacking faults (SFs) in 4H-SiC epitaxial wafers were inspected by using a mirror projection electron microscope (MPJ) [1, 2]. Dark and bright line contrasts of SFs in MPJ images represent surface morphology and crystal defects located in the epitaxial layer. Inspected SFs were classified into three types of SFs on the basis of the MPJ images. After classification, a cross section of each type of SF was observed by transmission electron microscopy (TEM) to verify the classification result. Complex SFs classified by MPJ images consisted of prismatic plane and basal plane SFs.

Microstructure of Stacking Fault Complex/Carrot Defects at Interface Between 4H-SiC Epitaxial Layers and Substrates

A carrot defect with a shallow pit has been detected in a 4H-SiC epitaxial wafer using mirror projection electron microscopy inspection. The origin of the carrot defect and the microstructure of the conversion point at the interface between the epitaxial layer and the substrate were investigated using transmission electron microscopy and high-resolution scanning transmission electron microscopy. We found that two types of threading edge dislocations (TEDs) in the substrate, with $$ {\varvec b} = 1/3\left[ {\bar{2}110} \right] $$ and $$ {\varvec b} = 1/3\left[ {\bar{1}\bar{1}20} \right] $$ , generated the carrot defect with a shallow pit in the epitaxial layer. The two TEDs converted to basal plane dislocations (BPDs) at the conversion point. Furthermore, one of the two BPDs led to the pair generation of a threading dislocation running to the epi surface and four partial dislocations propagating on each basal plane. The other BPD joined one of the four partial dislocations at the conversion point; this merged dislocation was assumed to cause a prismatic stacking fault.

Advances in High-Resolution Radiation Detection Using 4H-SiC Epitaxial Layer Devices.

Advances towards achieving the goal of miniature 4H-SiC based radiation detectors for harsh environment application have been studied extensively and reviewed in this article. The miniaturized devices were developed at the University of South Carolina (UofSC) on 8 × 8 mm 4H-SiC epitaxial layer wafers with an active area of ≈11 mm2. The thicknesses of the actual epitaxial layers were either 20 or 50 µm. The article reviews the investigation of defect levels in 4H-SiC epilayers and radiation detection properties of Schottky barrier devices (SBDs) fabricated in our laboratories at UofSC. Our studies led to the development of miniature SBDs with superior quality radiation detectors with highest reported energy resolution for alpha particles. The primary findings of this article shed light on defect identification in 4H-SiC epilayers and their correlation with the radiation detection properties.