Evaluation of Line-Shape Defect in Epitaxial Wafer

Abstract

In this study, we investigated the origin of line-shape defect in 4H-SiC epitaxial wafers. The inspection results revealed that such defects resulted from the substrate entirely and accompanied with dislocation lines during the epitaxial process. Although the defect surface condition with nanometer level of roughness seemed to do little harm to the initial electrical characteristics of power devices, dislocation lines possibly resulted in high leakage current when reverse voltage was applied. To reduce line-shape defects, it is essential to reduce defects and threading dislocations in substrates and to develop a nondestructive method for wafer screening.