4H-SiC Epitaxial Wafers Research Articles

Step-Bunching Dependence of the Lifetime of MOS Capacitor on 4<sup>o</sup> Off-Axis Si-Face 4H-SiC Epitaxial Wafers

The step-bunching dependence of the lifetime of metal–oxide–semiconductor capacitors on 4° off-axis 4H-SiC epitaxial wafers was investigated. The effects of the C/Si ratios in epitaxial growth and the substrate properties were examined. Step-bunching was observed at the base of triangle or trapezoid defects. Step-bunching decreased as the C/Si ratio was reduced. Time-dependent dielectric breakdown (TDDB) measurements showed that the locations of short lifetime breakdowns closely matched step-bunching positions. TDDB measurements of four different commercial substrates showed clear differences in capacitor lifetime.

Application of x-ray phase plate to grazing incidence x-ray topography for the control of penetration depth

The penetration depth of x-rays into a crystal is one of the most important parameters in grazing incidence x-ray topography. In this paper, we introduce a novel method for controlling the penetration depth by modifying the polarization of incident x-rays with fixed sample geometry and x-ray wavelength. We employed an x-ray phase plate in transmission geometry for controlling the polarization, and obtained x-ray topographs of an ion-implanted 4H–SiC epitaxial wafer with σ- and π-polarized x-rays. By comparing the two topographs, it was verified that the penetration depth of σ-polarization is smaller than that of π-polarization.

Characterization of (4,4)- and (5,3)-Type Stacking-Faults in 4deg.-Off 4H-SiC Epitaxial Wafers by Synchrotron X-Ray Topography and by Photo-Luminescence Spectroscopy

Experimentally,the grazing-incident X-ray topography at different diffraction conditions, and room temperature photo-luminescence spectroscopy, various different types of stacking-faults in epitaxial films on 4-degrees-off 4H-SiC wafers were identified precisely without wafer cutting. Their types and the numbers were investigated statistically. It became clear that (4,4) type stacking-faults were the most common ones and two different types were identified. Still 34% of the stacking-faults were unknown types in the present investigation.Several different kinds of stacking-faults formed on the surface of 4-degrees-off 4H-SiC epitaxial wafers were investigated. Their types could be identified and type distribution in a wafer could be obtained using X-ray topography and room temperature Photo-Luminescence without wafer cutting. Type determination of 8H(4,4)- stacking fault ; with or without strain field, could also be decideddemonstrated using this method.

Origin Analyses of Obtuse Triangular Defects in 4deg.-Off 4H-SiC Epitaxial Wafers by Electron Microscopy and by Synchrotron X-Ray Topography

Triangular shaped defects with obtuse-angles at tops and long bases are often observed in surfaces of epitaxial films. We have investigated the origins of them, and it became clear that these defects without clear origins were formed by contaminations of tantalum carbide particles. Formations of micro-order pipes at the origin points of these defects were also observed. These micro-order pipes did not accompany strain and dislocations around them, though their appearances were very similar to the ones so-called micro-pipes.

Characterization of Triangular-Defects in 4° off 4H-SiC Epitaxial Wafers by Synchrotron X-Ray Topography and by Transmission Electron Microscopy

We report our investigation results on triangular-defects formed on 4deg. off 4H-SiC epi- taxial wafers. Triangular-defects that had neither down-falls nor basal-plane dislocations previously reported as origins of triangular-defects at the tips of triangle were investigated by TEM. Our TEM results revealed that foreign materials contamination that were different from well-known down- -falls in size and in composition caused one of the defect formations and abnormal domain forma- tions were implied to occur and thought to relate to defect formations. We also report that several types of microstructure existed in the isosceles of defect during dislocation analyses around triangular-defects by X-ray topography.

Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts

Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.

Carrier Generation Lifetime in 4H-SiC Epitaxial Wafers

The pulsed MOS-C (Metal Oxide Semiconductor-Capacitor) technique was used to measure generation lifetimes in 4H-SiC epitaxial wafers. The ratio of generation to recombination lifetime has been investigated to understand the dominant defect for generation lifetime. The EH6/7 defect level is considered to limit generation lifetime and field enhanced emission is proposed to explain extremely large variation of generation lifetime in a small area. Generation lifetime is limited by dislocations when they are above a threshold density of about 106cm-2. Generation lifetimes measured on 4 and 8 degree off-cut angle epi-substrates are very comparable.

Silicon Carbide Vertical JFET Operating at High Temperature

Trenched and implanted vertical JFETs (TI-VJFETs) with blocking voltages of 700 V were fabricated on commercial 4H-SiC epitaxial wafers. Vertical p+-n junctions were formed by aluminium implantation in sidewalls of strip-like mesa structures. Normally-on 4H-SiC TI-VJFETs had specific on-state resistance (RO-S ) of 8 mW×cm2 measured at room temperature. These devices operated reversibly at a current density of 100 A/cm2 whilst placed on a hot stage at temperature of 500 °C and without any protective atmosphere. The change of RO-S with temperature rising from 20 to 500 °C followed a power law (~ T 2.4) which is close to the temperature dependence of electron mobility in 4H-SiC.

Carrier Lifetime Analysis by Microwave Photoconductive Decay (μ-PCD) for 4H SiC Epitaxial Wafers

Excess carrier lifetimes in 4H SiC epitaxial wafers were characterized by microwave photoconductive decay (o/PCD). The measured decay compromised of surface and bulk recombination curves have fast and slow components. Measured lifetimes are not changed with various surface passivation techniques. High resolution lifetime maps show good correlation with stress birefringence images and lower lifetime around extended material defects like grainboundaries, defect clusters, edge defects and polytype switching bands. Chlorosilane based CVD epiwafers show higher bulk lifetime values than standard silane based CVD materials due to less bulk lifetime defect density.

Dislocation in 4H n<sup>+</sup> SiC Substrates and their Relationship with Epilayer Defects

Several morphological defects in 4H SiC epitaxial wafers, including Comets and Triangles, may significantly impact on the yield and reliability of SiC devices. The formation of these epilayer defects is closely related to the substrate quality. This paper focuses on the study of the substrate quality and its relationship with defects in the epilayers. The crystalline quality of 4H n+ substrates has been characterized by x-ray diffraction, and the distribution of dislocations has been determined using etching in molten KOH. The relationship between Comet and Triangle epilayer defects and the dislocations has been established. A 10-fold reduction in the overall dislocation density in the 4H SiC substrates was achieved through technological improvements. The improvement was validated by the reduction in the number of the epilayer defects.

Nondestructive Analysis of Stacking Faults in 4H-SiC Bulk Wafers by Room-Temperature Photoluminescence Mapping under Deep UV Excitation

The advantage of room-temperature photoluminescence (PL) mapping was demonstrated for nondestructive detection of stacking faults (SFs) in off-oriented 4H-SiC epitaxial and bulk wafers. In mapping of the SF-related emission at 2.9 eV on the wafers, the SFs in the surface region appeared as a bar-shaped pattern with the long side perpendicular to the off-cut direction. The use of 266 nm light excitation is essential to detect the SF pattern in the bulk wafers because of its shallow penetration depth. The dark lines crossing the bar-shaped patterns in the epitaxial wafers are ascribable to the basal plane dislocation located close to the SF-planes.

High Voltage Silicon Carbide Schottky Diodes with Single Zone Junction Termination Extension

High voltage 4H-SiC Schottky diodes with single-zone junction termination extension (JTE) have been fabricated and characterised. Commercial 4H-SiC epitaxial wafers with 10, 20 and 45 +m thick n layers (with donor concentrations of 3×1015, 8×1014 and 8×1014 cm-3, respectively) were used. Boron implants annealed under argon flow at 1500°C for 30 minutes, without any additional protection of the SiC surface, were used to form JTE’s. After annealing, the total charge in the JTE was tuned by reactive ion etching. Diodes with molybdenum Schottky contacts exhibited maximum reverse voltages of 1.45, 3.3 and 6.7 kV, representing more than 80% of the ideal avalanche breakdown voltages and corresponding to a maximum parallel-plane electric field of 1.8 MV/cm. Diodes with a contact size of 1×1 mm were formed on 10 +m thick layers (production grade) using the same device processing. Characterisation of the diodes across a quarter of a 2-inch wafer gave an average value of 1.21 eV for barrier heights and 1.18 for ideality factors. The diodes exhibited blocking voltages (defined as the maximum voltage at which reverse current does not exceed 0.1 mA) higher than 1 kV with a yield of 21 %.

Current Analysis of Ion Implanted p<sup>+</sup>/n 4H-SiC Junctions: Post-Implantation Annealing in Ar Ambient

An n-type 8° off-axis <0001> 4H-SiC epitaxial wafer was processed. The n-type epilayer had doping and thickness of, respectively, ~3 × 1015 cm-3 and ~5 μm. p+/n diodes with not terminated junctions were constructed by a selective area implantation process of 9.2 × 1014 cm-2 Al+ ions at 400°C. The diodes had areas in the range 2×10-4 -1×10-3 cm2. The Al depth profile was 6×1019 cm-3 high and 164 nm thick. The post implantation annealing process was done in a high purity Ar ambient at 1600°C for 30 min. The diode current-voltage characteristics were measured in the temperature range 25-290°C. Statistics of 50-100 measurements per device type were done. The fraction of diodes that could be modeled as abrupt junctions within the frame of the Shockley theory decreased with increasing area value, but was always > 75%. The ideality factor was > 2 only at temperatures > 200°C and bias values < 1 V. The leakage current was extremely weak and remained of the order of 10-9 Acm-2 at 70°C and 500 V reverse bias. 4% of the diodes reached the theoretical voltage breakdown that was 1030 V. The surface roughness of un-implanted and implanted regions after diode processing was, respectively, 2 nm and 12 nm.

Correlation between reliability of thermal oxides and dislocations in n-type 4H-SiC epitaxial wafers

The correlation between thermal oxide reliability and dislocations in n-type 4H-SiC (0001) epitaxial wafers has been investigated. The thermal oxides were grown by dry oxidation at 1200°C followed by nitrogen postoxidation annealing. Charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations in a gate-oxide-forming area. Two types of dielectric breakdown modes, edge breakdown and dislocation-related breakdown, were confirmed by Nomarski microscopy. In addition, it is revealed that basal plane dislocation is the most common cause of the dislocation-related breakdown mode.

Defect-driven inhomogeneities in Ni∕4H–SiC Schottky barriers

Nanoscale depth-resolved cathodoluminescence spectroscopy (DRCLS) of Ni diode arrays on 4H-SiC epitaxial wafers reveals a striking correspondence between deep level defects and electrical transport measurements on a diode-by-diode basis. Current-voltage measurements display both ideal and nonideal diode characteristics due to multiple barriers within individual contacts. Near-interface DRCLS demonstrates the presence of three discrete midgap defect levels with 2.2, 2.45, and 2.65eV emission energies whose concentrations vary on a submicron scale among and within individual diodes, correlating with barrier inhomogeneity. These results also suggest that SiC native defect levels can account for the maximum range of n-type barrier heights.

Device processing and characterisation of high temperature silicon carbide Schottky diodes

High temperature silicon carbide diodes with nickel silicide Schottky contacts were fabricated by deposition of titanium–nickel metal film on 4H-SiC epitaxial wafer followed by annealing at 550 °C in vacuum. Room temperature boron implantation have been used to form single zone junction termination extension. 4H-SiC epitaxial structures designed to have theoretical parallel-plain breakdown voltages of 1900 and 3600 V have been used for this research. The diodes revealed soft recoverable avalanche breakdown at voltages of 1450 and 3400 V, respectively, which are about 80% and 95% of theoretical values. I– V characteristics of fabricated 4H-SiC Schottky diodes have been measured at temperatures from room temperature up to 400 °C. The diodes revealed unchangeable barrier heights and ideality factors as well as positive coefficients of breakdown voltage.

Effects of Dislocations on Reliability of Thermal Oxides Grown on n-Type 4H-SiC Wafer

The effects of dislocations in n-type 4H-SiC(0001) epitaxial wafers on the reliability of thermal oxides have been investigated. Charge-to-breakdown (QBD) values of thermal oxides decrease with increase in the dislocations under a gate-oxide area. Nomarski microscope observations show that dielectric breakdown of thermal oxides occurs at the position of dislocation in epitaxial layer. It is reavealed that basal plane dislocation is the most common cause of the dielectric breakdown.

Protection of selectively implanted and patterned silicon carbide surfaces with graphite capping layer during post-implantation annealing

A graphite capping layer has been evaluated to protect the surface of patterned and selectively implanted 4H–SiC epitaxial wafers during post-implantation annealing. AZ-5214E photoresist was spun and baked in vacuum at temperatures ranging from 750 to 850 °C to form a continuous coating on both planar and mesa-etched SiC surfaces with features up to 2 µm in height. Complete conversion of the hydrogenated polymer-like film into nanocrystalline graphite layer was verified by Raman spectroscopy. The graphite capping layer remained undamaged and protected both planar and mesa-etched SiC surfaces during subsequent annealing in argon ambient at temperatures up to 1650 °C for 30 min. It effectively suppressed step bunching and dopant out-diffusion in implanted regions and simultaneously ensured that the un-implanted surface of the 4H–SiC epitaxial wafer remained free of contamination. Schottky barrier diodes formed on the un-implanted annealed surfaces displayed almost ideal characteristics.

Effects of n-type 4H-SiC epitaxial wafer quality on reliability of thermal oxides

The reliability of thermal oxides was investigated on n-type 4H-SiC(0001) epitaxial wafers with different metal impurity concentrations and surface roughness. Time-zero dielectric breakdown measurements showed that almost all of the thermal oxides ruptured at a field-to-breakdown (EBD) of 10MV∕cm, and that the maximum EBD was 11MV∕cm, despite the influence of the epitaxial wafer. On the other hand, time-dependent dielectric breakdown measurements indicated that the charge-to-breakdown (QBD) of the thermal oxides was influenced by the epitaxial wafer. This suggests that two types of oxide breakdown regimes exist under a high-stress field: one resulting from wafer influences, and the other intrinsic.

Microscopic defects and homogeneity investigations in 4H-SiC epitaxial wafers by UV scanning photoluminescence spectroscopy

UV scanning photoluminescence spectroscopy is applied to 4H-SiC epitaxy characterization. In a first part, the technique is used for triangular defects characterization. The results show that two kinds of defects are present. Some defects are inclusion of cubic SiC which is confirmed by Raman spectroscopy. The other ones consist of staking faults of different thicknesses acting as quantum wells. In a second part, the effective lifetime profile is mapped for a whole 50 mm epitaxy using the variation of room temperature PL intensity versus excitation intensity.