1-bit Comparator Research Articles

A Novel Design of 12-bit Digital Comparator Using Multiplexer for High Speed Application in 32-nm CMOS Technology

In the present scenario, power, speed, and area of an electronic device play a significant role specifically in the field of modern VLSI technology. In this research, small power dissipation and a less area-based single 12-bit comparator has been designed using a multiplexer. To improve the speed of the comparator a completely unique technique has applied, where three 4-bit comparator blocks have been used rather than a single 12-bit comparator. These comparator blocks compare simultaneously two signals each having 4-bits. The aim of this paper is to design and implement a 2-bit digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. Finally, the novel technique has been applied to improve the overall performance of a 12-bit comparator. The results of this paper are simulated on the EDA tanner tool realized in 32-nanometer technology at 0.7 V supply voltage. It shows that the propagation delay of 12-bit digital comparator using the novel technique is 5.15 nanoseconds which is approximately 30% less than the proposed multiplexer-based single 12-bit comparator.

A Novel Very Low-Complexity Multi-valued Logic Comparator in Nanoelectronics

Using multi-valued logic (MVL) can reduce chip connections, which can have a direct effect on the chip area and connections power consumption. In the recent years, due to the high capability of nanotechnology in designing MVLs, some researchers have focused on this field. In designing MVL circuits, the low-complexity design is of great importance to fulfill the MVL aim. In this paper, a very low-complexity comparator for the MVL is proposed based on the multi-threshold voltage in CNTFETs. The proposed comparator in the 1-bit greater function only needs four transistors for all multi-valued logics; this results in a considerable transistor count reduction in comparison with the pervious works relying on 32 and 50 transistors in a ternary to quaternary case, respectively. Also, the number of 1-bit comparators is reduced from 50 and 74 transistors for the ternary to quaternary cases in the previous works to 12 in the proposed design. Additionally, the multi-digit comparator using the novel digit comparator is proposed. The simulation results using the Stanford 32 nm CNTFET library in HSPICE confirm the proper operation of the proposed comparator with the same range in PDP, in comparison with the previous works.

A novel proposal for all-optical 1-bit comparator using nonlinear PhCRRs

All-optical comparators play crucial roles in all-optical data processing systems. In this paper, we proposed a novel structure for realizing an all-optical comparator, which can compare two 1-bit binary codes. For this purpose, we used three nonlinear resonant rings. The final structure has two input and three output ports. The maximum rise and fall times for the proposed structure are about 1.5 and 2 ps, respectively.

A novel proposal for all optical 1-bit comparator using nonlinear PhCRRs

All optical comparators play crucial roles in all optical data processing systems. In this paper we proposed a novel structure for realizing an all optical comparator, which can compares two 1-bit binary codes. For this purpose we used 4 nonlinear resonant rings. The final structure has two input –namely X and Y_ and three output ports –namely F1, F2 and F3-. The maximum time delay of the proposed structure is about 6 ps. The results show that, when X and Y are the same, only F3 is ON, when X is ON and Y is OFF, only F1 is ON and finally when Y is ON and X is OFF, only F2 is ON.

Design of efficient coplanar 1-bit comparator circuit in QCA technology

QCA technology is an emerging and promising technology for implementation of digital circuits in nano-scale. The comparator circuits play an important role in digital circuits. In this work, a new and efficient coplanar 1-bit comparator circuit is proposed and evaluated in the QCA technology. The designed coplanar 1-bit QCA comparator circuit is constructed based on majority gate, XNOR gate and inverter gate that are designed carefully. The functionality of the designed coplanar 1-bit QCA comparator circuit is verified by using QCADesigner version 2.0.3. The obtained results indicate that the designed 1-bit QCA comparator circuit requires 0.03 ?m2 area and 38 QCA cells. It also has 0.5 clock cycles delay. The comparison demonstrates that the designed QCA comparator circuit provides improvements in comparison with other QCA comparator circuits in terms of effective area, cell count, and delay as well as cost.

Continuous-Time Delta-Sigma Modulators Based on Passive RC Integrators

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators ( $\Delta \Sigma $ Ms) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the $\Delta \Sigma \text{M}$ loop filter. A third-order CT $\Delta \Sigma \text{M}$ is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS $\Delta \Sigma \text{M}$ occupies only $0.013~\mathrm {mm^{2}}$ , dissipates 256 $\mu \text{W}$ from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a $\mathrm {FoM_{Schreier}}$ of 175.1 dB.

Design and simulation of an all optical photonic crystal-based comparator

Optical comparators are essential elements required for creating all optical digital systems used in optical data processing. A new structure is proposed for designing a 1-bit optical comparators using nonlinear photonic crystal ring resonators. The nonlinear photonic crystal ring resonators are created by adding some additional dielectric rods around the core section of the resonant ring. These rods are made of doped glass which has relatively high Kerr coefficient. Four nonlinear resonant rings are used with optical waveguides to create the proposed comparator inside a 2D photonic crystal structure. The final structure can compare two 1-bit numbers. The maximum delay time and total footprint of the proposed structure is 6 ps and 1705 μm2, respectively.

1-bit and 2-bit Comparator Designs and Analyses for Quantum-Dot Cellular Automata

In computerized PCs number of arithmetic operations, the comparator is the vital equipment unit, composed of CMOS innovation. Another procedure named as Quantum Cellular Automata (QCA) will supplant the CMOS outlines, having leverage concerning zone, control utilization, and latency. The primary QCA circuits planned with the inverter and majority voter entryways. In this paper, we utilize the clocking method 180º out of phase clock hybrid to outline the 1-bit comparator and contrast and the current outcomes. The new proposed wire crossing plan lessens the quantity of cells required to configuration, power and area necessities. Besides, we planned 2-bit comparator with 11 number of majority voters, 2 number of crossovers with 0.38 um^2 area, 203 number of cells. The designed 1-bit comparator contrast and the past outcomes where cells, region, defer demonstrates 53.57%, 50%, 33.32% improvement respectively.

1-bit and 2-bit comparator designs and analysis for quantum-dot cellular automata

1-bit and 2-bit comparator designs and analysis for quantum-dot cellular automata

FPGA Logic Circuit Implementation and Synthesis with VHDL Programming: A Learning Approach

There are significant numbers of relevant research works available that concerns VHDL programming and Field Programmable Gate Array (FPGA) based hardware design, simulation and implementation. This is because; both the FPGA design and VHDL programming realization are quiet new and useful to accomplish various tasks in the field of research for digital system designed and development of miniaturized embedded system. It is found difficult to understand and put into practice by the learners in the tertiary institution, which still requires rapid training and development. In this paper, we design and demonstrate an FPGAlogic circuit using 4-bit BCD adders and parallel 4-bit comparator with a stepwise development of the vital soft logic design flow, simulation and timing analysis. It also presents an educational concept designed for complementing courses offered like FPGA prototype and ASIC design. This perception of FPGA-based design flow will facilitate learner’s understanding, skills and it will provide detailed insights into various aspects of microelectronics, digital logic systems design and VHDL programming. Keywords: Behavioral synthesis, BCD Adder, Four-bit comparator, FPGA prototype, Hardware design, Microelectronic, VHDL programming.

Design and Implementation of Quantum Dot Cellular Automata Based Irreversible and Reversible Logic Generator Block

Quantum Dot Cellular Automata has attracted a lot of attention due to its extremely small feature size and ultra low power consumption. It is a possible alternative for transistor based technology. This paper presents the construction of Irreversible and reversible Logic Generator Block using quantum dot cellular automata. QCA based Irreversible and irreversible Logic generator block generates the logic of various devices like 1-Bit comparator, 1-Bit Half Adder, 1-Bit Half Subtractor, AND gate, XOR gate, NOR gate and XNOR gate. Proposed design of QCA based LGB is cost effective and easy to fabricate due to absence of wire crossings in irreversible LGB and no information loss in reversible LGB. This block can be made more efficient by using control lines. Depending on individual value on control line, logic of individual device will be generated. QCADesigner 2.0.3 tool is used for design and simulation of QCA based Logic Generator Block. Similarly here Reversible logic based Logic generator block is proposed which will be able to generate different logic. Area requirement of Reversible LGB is 85% less as compared to Irreversible LGB. Reversible logic provides ideally zero power dissipation that is no information loss is there.

One-bit in-phase observation for direct learning-based digital predistortion with modified frequency-domain delay estimation and alignment

This article proposes a novel digital predistortion (DPD) implementation method for RF power amplifiers. The new approach adopts only one 1-bit comparator in the feedback path to observe the in-phase (I) or the quadrature (Q) component of the error signal between the input and the output signals. To this end, the theoretical derivation of the in-phase observation based on direct learning architecture (DLA) DPD is first given in this article, by combining the existing 1-bit method and the low-cost in-phase observation. To facilitate the delay estimation and alignment, a modified iterative frequency-domain delay estimation is presented, which only acquires either I or Q components of the output signal to achieve satisfied delay estimation. Experimental results show that the proposed DPD method decreased the normalized mean square error (NMSE) and the adjacent channel power ratio (ACPR) to less than −42 and −51 dB, respectively, which indicates that the proposed DPD system can achieve comparable performance as the existing DPD identification techniques with lower implementation complexity.

1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers

In this paper, we propose a low-cost data-acquisition approach for model extraction of digital predistortion (DPD) of RF power amplifiers. The proposed approach utilizes only 1-bit-resolution analog-to-digital converters (ADCs) in the observation path to digitize the error signal between the input and output signals. The DPD coefficients are then estimated based on the direct learning architecture using the measured signs of the error signal. The proposed solution is proved feasible in theory, and the experimental results show that the proposed algorithm achieves the performance equivalent to that using the conventional method. Replacing high-resolution ADCs with 1-bit comparators in the feedback path can dramatically reduce the power consumption and cost of the DPD system. The 1-bit solution also makes DPD become practically implementable in future broadband systems since it is relatively straightforward to achieve an ultrahigh sampling speed in data conversion using only simple comparators.

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13μm technology with the supply voltage of 1V.

Design and Implementation of 1-bit Comparator in Quantum-dot Cellular Automata (QCA)

Abstract . For immense demand of speedy high-end gadgets, chips are becoming denser, but Moore's law is falling flat lately. Complementary Metal-Oxide-Semiconductor (CMOS) technology is on its brink. Quantum-dot cellular automata (QCA) has become a potential alternative technology to provide faster speed with low power dissipation at nano-scale extent. Here, we proposed an efficient QCA design of 1-bit comparator. The proposed comparator required 59% less area and dissipated 82% less energy. QCADesigner has been used to design and simulate the proposed comparator. Finally, QCAPro tool has been employed for estimating energy dissipation. Keywords: Comparator, Energy dissipation, QCA Designer, QCAPro

Chaotic laser-based ultrafast multi-bit physical random number generation without post-process

Random numbers have great application value in the fields of secure communications, which are commonly used as secret keys to encrypt the information. To guarantee that the information is absolutely secure in the current high-speed communication, the applied random keys should possess a generation speed not less than the encrypted data rate, according to one-time pad theory found by Shannon (Shannon C E 1949 Bell.Syst.Tech.J. 28 656) Pseudo-random numbers generated by algorithm may easily reach a fast speed, but a certain periodicity makes them difficult to meet the aforementioned demand of information security. Utilizing physical stochastic phenomena can provide reliable random numbers, called physical random number generators (RNGs). However, limited by the bandwidth of the conventional physical sources such as electronic noise, frequency jitter of oscillator and quantum randomness, the traditional physical RNG has a generation speed at a level of Mb/s typically. Therefore, real-time and ultrafast physical random number generation is urgently required from the view of absolute security for high-speed communication today. With the advent of wideband photonic entropy sources, in recent years lots of schemes for high-speed random number generation are proposed. Among them, chaotic laser has received great attention due to its ultra-wide bandwidth and large random fluctuation of intensity. The real-time speed of physical RNG based on chaotic laser is now limited under 5 Gb/s, although the reported RNG claims that an ultrafast speed of Tb/s is possible in theory. The main issues that restrict the real-time speed of RNG based on chaotic laser are from two aspects. The first aspect is electrical jitter bottleneck confronted by the electrical analog-to-digital converter (ADC). Specifically, most of the methods of extracting random numbers are first to convert the chaotic laser into an electrical signal by a photo-detector, then use an electrical ADC driven by radio frequency (RF) clock to sample and quantify the chaotic signal in electronic domain. Unfortunately, the response rate of ADC is below Gb/s restricted by the aperture jitter (several picoseconds) of RF clock in the sample and hold circuit. The second aspect comes from the complex post-processes, which are fundamental in current RNG techniques to realize a good randomness. The strict synchronization among post-processing components (e.g., XOR gates, memory buffers, high-order difference) is controlled by an RF clock. Similarly, it is also an insurmountable obstacle to achieve an accurate synchronization due to the electronic jitter of the RF clock. In this paper, we propose a method of ultrafast multi-bit physical RNG based on chaotic laser without any post-process. In this method, a train of optical pulses generated by a GHz mode-locked laser with low temporal jitter at a level of fs is used as an optical sampling clock. The chaotic laser is sampled in the optical domain through a low switching energy and high-linearity terahertz optical asymmetric demultiplexer (TOAD) sampler, which is a fiber loop with an asymmetrical nonlinear semiconductor optical amplifier. Then, the peak amplitude of each sampled chaotic pulse is digitized by a multi-bit comparator (i.e., a multi-bit ADC without sample and hold circuit) and converted into random numbers directly. Specifically, a proof-of-principle experiment is executed to demonstrate the aforementioned proposed method. In this experiment, an optical feedback chaotic laser is used, which has a bandwidth of 6 GHz. Through setting a sampling rate to be 5 GSa/s and selecting 4 LSBs outputs of the 8-bit comparator, 20 Gb/s (=5 GSa/s4 LSBs) physical random number sequences are obtained. Considering the ultrafast response rate of TOAD sampler, the speed of random numbers generated by this method has the potential to reach several hundreds of Gb/s as long as the used chaotic laser has a sufficient bandwidth.

Optimized design and performance analysis of novel comparator and full adder in nanoscale

AbstractIn a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimitable transistorless computation approach that is based on semiconductor substantial and a substitute for customary CMOS and VLSI archetype at nanoscale point which comprises a better switching frequency, enhanced scale integration and small extent. In the design of digital logic, a comparator is the essential forming component which implements the resemblance of two numbers and a binary full adder is a major entity in digital logic systems. This paper deals with an expanded layout of reversible 1-bit comparator and proficient full adder without wire-crossing in QCA. The proposed layouts are significantly declined in terms of area and cell complexity, assessed to other layouts and clock cycle is retained at least. Quantum costs of the proposed circuits are es...

A Low-Power and Area-Efficient 64-Bit Digital Comparator

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90[Formula: see text]nm 1.2[Formula: see text]V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009[Formula: see text][Formula: see text], a worst case delay of 858[Formula: see text]ps, and a power consumption of 898[Formula: see text]uW at 1[Formula: see text]G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600[Formula: see text][Formula: see text]) of the total comparator area and contributes 54% (484[Formula: see text][Formula: see text]W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

Reversible Comparator Design Using Quantum Dot-Cellular Automata

ABSTRACTQuantum dot-cellular automata (QCA) emerge as a research area to design nanometre scale logic circuit. In digital logic design, a comparator is the fundamental building block that performs the comparison of two numbers. This paper deals with the design of reversible building block for 1-bit comparator and its implementation in QCA. An improved QCA layout of Feynman gate is also achieved. The QCA Feynman gate is denser and has low delay than the existing circuit. The proposed reversible comparator has quantum cost 9, whereas the QCA reversible comparator has the quantum cost 0.927. The quantum cost based comparison of the proposed QCA reversible comparator with conventional reversible comparator shows the cost effective circuit design in QCA. The simulation result matched the truth table of comparator which approves the functional capability of the proposed QCA layout of comparator. All the proposed layouts dissipate very low power.

Design of 1-bit and 2-bit magnitude comparators using electro-optic effect in Mach–Zehnder interferometers

The Mach–Zehnder interferometer (MZI) structures collectively show powerful capability in switching an input optical signal to a desired output port from a collection of output ports. Hence, it is possible to construct complex optical combinational digital circuits using the electro-optic effect constituting MZI structure as a basic building block. Optical switches have been designed for 1-bit and 2-bit magnitude comparators based on electro-optic effect using Mach–Zehnder interferometers. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. Analysis of some factors influencing the performances of proposed device has been discussed properly. The study is verified using beam propagation method.