1-bit Comparator Research Articles

A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources

The test of analog & RF circuits at wafer-level suffers from both quality and throughput limitations, especially due to probing issues and limited count of expensive instrumentation resources. Since final test after packaging guarantees product performances, constraints on wafer-level test can be relaxed. This paper investigates a signal acquisition protocol based on the use of digital tester channels to perform the demodulation of analog/RF signals. Due to the large availability of such hardware resources on most testers, this approach allows to setup a multi-site strategy, thus increasing the test throughput. The fundamental concept is to capture the signal through the 1-bit comparator available in a digital tester channel and to process the resulting bit stream to retrieve the analog/RF signal characteristics. In this paper, the proposed solution is illustrated for the demodulation of Frequency-Modulated (FM) and Amplitude-Modulated (AM) signals. Both simulation and experimental results obtained with a Verigy 93K platform are presented.

A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing

We propose a novel strategy to optimize the test suite required for testing both hardware and software in a production line. Here, the strategy is based on two processes: Quality Signing Process and Quality Verification Process, respectively. Unlike earlier work, the proposed strategy is based on integration of black box and white box techniques in order to derive an optimum test suite during the Quality Signing Process. In this case, the generated optimal test suite significantly improves the Quality Verification Process. Considering both processes, the novelty of the proposed strategy is the fact that the optimization and reduction of test suite is performed by selecting only mutant killing test cases from cumulating t-way test cases. As such, the proposed strategy can potentially enhance the quality of product with minimal cost in terms of overall resource usage and time execution. As a case study, this paper describes the step-by-step application of the strategy for testing a 4-bit Magnitude Comparator Integrated Circuits in a production line. Comparatively, our result demonstrates that the proposed strategy outperforms the traditional block partitioning strategy with the mutant score of 100% to 90%, respectively, with the same number of test cases.

ALL-OPTICAL TERAHERTZ OPTICAL ASYMMETRIC DEMULTIPLEXER (TOAD) BASED BINARY COMPARATOR: A PROPOSAL

Comparator determines whether a number is greater than, equals to or less than another number. It plays a significant role in fast central processing unit in all-optical scheme. In all-optical scheme here 1-bit binary comparator is proposed and described by Terahertz Optical Asymmetric Demultiplexer (TOAD) based interferometric switch. Simulation result by Mathcad-7 is also given. Cascading technique of building up the n-bit binary comparator with this 1-bit comparator block is also proposed here.

Single-Flux-Quantum Circuit Based Readout System for Detector Arrays by Using Time to Digital Conversion

We propose a single-flux-quantum (SFQ) based readout circuit for a transition edge sensor (TES) array for X-ray radiation detection. Utilization of SFQ circuits for this purpose enables large-scale integration of TESs due to very high speed processing ability of the received signals and using an already established integrated circuit design environment. We utilize the cooling time dependence of the TES on the incident X-ray energy. Time to digital conversion is made by using an SFQ based quasi-one-junction SQUID (QOS), which works as a 1-bit comparator with an adjustable current threshold level, and an SFQ based high speed counter. The readout system is composed of two separate chips that are connected to each other with flexible superconducting wiring. The QOS-multiplexer chip is directly connected to the TES array and it performs the digital conversion of the TES output. The demultiplexer-counter chip, which will be placed at elevated temperatures, receives the multiplexed SFQ pulses and determines the duration of the TES output which is above the predetermined threshold level. Final goal of this work is to readout more than 10 k TES pixels and in this paper, feasibility of the system and current status of the development process is demonstrated.

10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계

본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다. This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonant tunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10/sup 6/ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit.

A new structure of EHW

Evolvable hardware (EHW) realizes circuit function through evolution. It may be viewed as the combination of EAs (evolutionary algorithms) and PLDs (programmable logic devices). At present the main problem is that the speed of evolution is too slow. In order to tackle the problem, we must do work from two aspects: algorithm and device structure. This paper presents a function PLD as a new EHW's structure. So the efficiency of coding is improved, and evolution is sped up. A 4-bit comparator is successfully completed.

1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking

A high-speed 64-bit comparator using two-phase clocking dynamic CMOS logic with modified noninverting all-N-transistor block is presented. The pull-up charging and pull-down discharging of a comparator unit are accelerated by inserting two feedback MOS transistors between the evaluation N-block and the output. Detailed simulation results reveal appropriate L/W guidelines for the all-N-transistor block design. To increase throughput a parallel tree structure with two-phase clocks is employed. The comparator units of two adjacent layers are triggered by two out-of-phase clocks so that their individual outputs are pipelined without using extra hardware, e.g. latches. The operating clock frequency is 1.0 GHz while the compared output of two 64-bit binary numbers is done in 3.5 cycles.