A Novel Design of 12-bit Digital Comparator Using Multiplexer for High Speed Application in 32-nm CMOS Technology

Abstract

In the present scenario, power, speed, and area of an electronic device play a significant role specifically in the field of modern VLSI technology. In this research, small power dissipation and a less area-based single 12-bit comparator has been designed using a multiplexer. To improve the speed of the comparator a completely unique technique has applied, where three 4-bit comparator blocks have been used rather than a single 12-bit comparator. These comparator blocks compare simultaneously two signals each having 4-bits. The aim of this paper is to design and implement a 2-bit digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. Finally, the novel technique has been applied to improve the overall performance of a 12-bit comparator. The results of this paper are simulated on the EDA tanner tool realized in 32-nanometer technology at 0.7 V supply voltage. It shows that the propagation delay of 12-bit digital comparator using the novel technique is 5.15 nanoseconds which is approximately 30% less than the proposed multiplexer-based single 12-bit comparator.