Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits

Abstract

A design technique based on optimizing the supply voltage for simultaneously achieving energy efficiency and temperature variation insensitive circuit performance is proposed in this paper. The supply voltages that suppress the propagation delay variations when the temperature fluctuates are identified for a diverse set of circuits in 180 and 65 nm CMOS technologies. Circuits display temperature variation insensitive propagation delay when operated at a supply voltage 44–47% lower than the nominal supply voltage ( V DD = 1.8 V ) in a 180 nm CMOS technology. Similarly, the optimum supply voltages are 67–68% lower than the nominal supply voltage ( V DD = 1.0 V ) in a 65 nm CMOS technology. At scaled supply voltages, integrated circuits consume lower power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive for low-power applications with relaxed speed requirements. A new design methodology based on threshold voltage optimization for achieving temperature variation insensitive circuit speed is also evaluated. The energy per cycle and the propagation delay at the supply and threshold voltages providing temperature variation insensitive circuit performance, minimum energy-delay product, and minimum energy are compared. Results indicate that low-power operation and temperature variation tolerance can be simultaneously achieved with the proposed techniques.