Voltage optimization for temperature variation insensitive CMOS circuits

Abstract

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature dependent propagation delay characteristics, as shown in this paper, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45 nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature variations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented in this paper. The optimum supply voltage is 45% to 57% lower than the nominal supply voltage in a 180 nm CMOS technology. Alternatively, the optimum supply voltage is 10% to 54% higher than the nominal supply voltage in a 45 nm CMOS technology. The gap between the optimum and nominal supply voltages increases in a low-power design. Deeply scaled low-power integrated circuits operating at ultra-low voltage supplies are, therefore, expected to be highly sensitive to temperature variations. Alternatively, the speed-centric determination of the supply voltage will be less catastrophic for maintaining the circuit reliability under temperature variations in the future technology generations