Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology

Abstract

A design methodology based on optimizing the supply voltage for simultaneously achieving energy efficiency and temperature variation insensitive circuit performance is presented in this paper. Circuits exhibit temperature variation insensitive delay characteristics when operated at a supply voltage 67% to 68% lower than the nominal supply voltage. At scaled supply voltages, integrated circuits consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive for low power applications with relaxed speed requirements. The supply voltages that yield minimum energy and minimum energy-delay product are identified at two different temperatures for circuits in a 65 nm CMOS technology. The energy and speed at the supply voltages providing temperature variation insensitive propagation delay, minimum energy, and minimum energy-delay product are compared. Results indicate that energy efficient integrated circuits with deeply scaled supply voltages can also be made insensitive to temperature fluctuations by considering the temperature dependence of speed in the supply voltage optimization process.