Continuous-Time Delta-Sigma Modulators Based on Passive RC Integrators

Abstract

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators ( $\Delta \Sigma $ Ms) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the $\Delta \Sigma \text{M}$ loop filter. A third-order CT $\Delta \Sigma \text{M}$ is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS $\Delta \Sigma \text{M}$ occupies only $0.013~\mathrm {mm^{2}}$ , dissipates 256 $\mu \text{W}$ from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a $\mathrm {FoM_{Schreier}}$ of 175.1 dB.