Abstract
A continuous-time (CT) delta-sigma modulator (ΔΣM), with 27.5 fJ/conv.-step energy efficiency, employing passive RC integrators is proposed. A simple differential pair is incorporated in the loop-filter between each passive RC integrator and, the extra required gain in the loop is obtained in the comparator. Due to the many design issues, such as the trade-off between RC variations and loop stability, the modulator is optimized using genetic algorithms (GAs). The 65 nm CMOS ΔΣM, occupying only 0.013 mm2, dissipates 256 μW from a 0.7 V supply and achieves a peak SNDR of 69.1 dB with 2 MHz bandwidth (BW). The dynamic range (DR) reaches 76.2 dB, which corresponds to a FoM Schreier of 175.1 dB.
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