Optimized design and performance analysis of novel comparator and full adder in nanoscale

Md Abdullah-Al-Shafi,Ali Newaz Bahar,Qingsong Ai

doi:10.1080/23311916.2016.1237864

Abstract

AbstractIn a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimitable transistorless computation approach that is based on semiconductor substantial and a substitute for customary CMOS and VLSI archetype at nanoscale point which comprises a better switching frequency, enhanced scale integration and small extent. In the design of digital logic, a comparator is the essential forming component which implements the resemblance of two numbers and a binary full adder is a major entity in digital logic systems. This paper deals with an expanded layout of reversible 1-bit comparator and proficient full adder without wire-crossing in QCA. The proposed layouts are significantly declined in terms of area and cell complexity, assessed to other layouts and clock cycle is retained at least. Quantum costs of the proposed circuits are es...

Highlights

In the proximate future, it is predictable that the usual CMOS archetype extends to the culmination of its roadmap due to numerous thoughtful disputes as impurity discrepancies, elevated outlay of lithography and more notably (Lent, Tougaw, Porod, & Bernstein, 1993; Tóth & Lent, 1999; Wilson, Kannangara Geoff Smith, Simmons, Raguse, & Raguse, 2002)
This paper proposed a new Quantum-dot Cellular Automata (QCA) comparator and full adder layout in single layer which is enriched in term of cell and area complexity in contrast to other designs (Abedi, Jaberipur, & Sangsefidi, 2015; Angizi, Alkaldy, Bagherzadeh, & Navi, 2014; Basha & Kumar, 2012; Cho, 2006; Cho & Swartzlander, 2009; Das & De, 2015; Dehghan, Roozbeh, & Zare, 2014; Hänninen & Takala, 2010; Hashemi & Navi, 2015; Kianpour, Sabbaghi-Nadooshan, & Navi, 2014; Kim, Wu, & Karri, 2007; Navi et al, 2010; Pudi & Sridharan, 2012; Vetteth et al, 2002)
Conceiving a durable and single layer QCA comparator and full-adder is of immense significance to construct arithmetic circuit design

Summary

Introduction

It is predictable that the usual CMOS archetype extends to the culmination of its roadmap due to numerous thoughtful disputes as impurity discrepancies, elevated outlay of lithography and more notably (Lent, Tougaw, Porod, & Bernstein, 1993; Tóth & Lent, 1999; Wilson, Kannangara Geoff Smith, Simmons, Raguse, & Raguse, 2002). This paper proposed a new QCA comparator and full adder layout in single layer which is enriched in term of cell and area complexity in contrast to other designs (Abedi, Jaberipur, & Sangsefidi, 2015; Angizi, Alkaldy, Bagherzadeh, & Navi, 2014; Basha & Kumar, 2012; Cho, 2006; Cho & Swartzlander, 2009; Das & De, 2015; Dehghan, Roozbeh, & Zare, 2014; Hänninen & Takala, 2010; Hashemi & Navi, 2015; Kianpour, Sabbaghi-Nadooshan, & Navi, 2014; Kim, Wu, & Karri, 2007; Navi et al, 2010; Pudi & Sridharan, 2012; Vetteth et al, 2002).

Methods and materials

Design

Findings

Conclusion