Abstract
AbstractFull adder and full subtractor are often a combinational logic circuit that performs three one-bit binary digits of addition and subtraction operations, respectively. Full adder is an important element for the development of different devices such as microprocessors and digital signal processors. The design of the area-efficient full adder is essential to build an area-efficient processor. In this paper, we have implemented an area-efficient full adder circuit and full subtractor circuit using quantum dot cellular automata (QCA). A better EX-OR gate configuration in terms of efficient area is chosen to create the full adder and full subtractor designs. The proposed full subtractor and full adder architecture requires 22 and 23 quantum cells, respectively, whose effective area is 0.0192 μm2 (micro-metre square) only. A tool called QCADesigner is used to implement the design and check its performance. The dissipation of energy is measured using the QCAD-E tool.KeywordsComplementary metal–oxide–semiconductor (CMOS) technologyExclusive-OR (EX-OR) gateFull adder (FA)Full subtractor (FS)Quantum dot cellular automata (QCA)QCADesigner
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