Xilinx Virtex-5 Field Programmable Gate Array Research Articles

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

HopliteRT: Real-Time NoC for FPGA

With the increasing number of computation nodes integrated in multi and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systems-on-chips (SoCs). HopliteRT is a new NoC design that was recently proposed to address the needs of real-time systems whilst respecting the constraints of field-programmable gate array (FPGA) platforms. In this article, we: 1) introduce priority-based routing in HopliteRT; 2) change the network topology in order to improve the packets' worst-case traversal time (WCTT); 3) identify a flaw in the existing timing analysis of HopliteRT; and 4) develop a new timing analysis that is proven correct. We also show by means of experiments that the modifications of HopliteRT proposed in this article allows for at least 2× improvement on the worst and average case traversal time of high priority packets, without impacting the quality of service of low-priority packets. The timing properties of high priority flows are greatly improved for negligible additional hardware costs. The proposed NoC has been implemented in Verilog and synthesized for a Xilinx Virtex-7 FPGA platform.

A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

FPGA-Based Deep Convolutional Neural Network of Process Adaptive VMD Data With Online Sequential RVFLN for Power Quality Events Recognition

In this article, self-adaptive variational mode decomposition (SAVMD), deep convolutional neural networks (DCNN), and online-sequential random vector functional link networks (OSRVFLN) are integrated to categorize the single as well as combined power quality events (PQEs) in real time. The SAVMD method is proposed to optimize both the number of decomposition and data-fidelity factor to extract the most efficient band-limited mode (BLM) based on entropy and Kurtosis index. The most discriminative unsupervised features are extracted automatically using a DCNN from the BLM of SAVMD. The extracted distinct feature vector is fed to the proposed supervised OSRVFLN classifier to train accurately by minimizing the training cross-entropy loss with an increment in the number of hidden nodes for obtaining the maximum classification accuracy of the complex PQE patterns in noisy and noise-free environments. The automatic efficacious feature extraction, superior classification accuracy, noise immunity, and short event detection time are the major advantages of the proposed SAVMD-DCNN-OSRVFLN method. Finally, the novel methodology is implemented in a fast digital Xilinx Virtex-5 field-programmable gate array embedded processor to validate the practicability and feasibility of the proposed method in real-time.

Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

PUF-Based Secure Chaotic Random Number Generator Design Methodology

Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis.

Design and implementation of hydrogen economy using artificial neural network on field programmable gate array

In this study, economic analysis of the hydrogen generation and liquefaction system has been modeled using Multi-Layer Feed-Forward Artificial Neural Network (MLFFANN) and implemented on Field Programmable Gate Array (FPGA). Firstly, the 100X6 data set has been created to be used in the ANN-based modeling of the system using the Engineering Equation Solver (EES) program. This data set has been divided into two data sets as 80X6 for training and 20X6 for testing. The structure of the ANN-based economic analysis of hydrogen generation and liquefaction has been composed of 3 neurons in the input layer, ten neurons in the hidden layer, and three neurons in the output layer. Elliott-2-based TanSig transfer function and Purelin transfer function have been used in the neurons of the hidden layer and the output layer, respectively. Then, the ANN-model has been trained and tested using the Matlab program. The MSE values, 1.40x10E-7 and 2.07x10E-5, have been obtained as the results of the training phase and test phase of the ANN-based system, respectively. After getting fruitful results from training and testing phases, the economic analyses of hydrogen generation and liquation systems have been modeled in VHDL using bias and weight values located in the constructed ANN-based system using Matlab. The modeling has been performed in the Xilinx ISE Design Tools program using a 32-bit IEEE-754-1985 floating-point number standard. Then, the modeled ANN-based economic analysis of the hydrogen generation and liquation system has been implemented on the Xilinx Virtex-7 FPGA chip by performing the Place&Route process. The maximum operating frequency of the ANN-based hydrogen generation and liquefaction economy system implemented on FPGA has been obtained as 281.702 MHz using Xilinx ISE Design Tools.

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

High Speed Partial Pattern Classification System Using a CAM-Based LBP Histogram on FPGA

This letter proposes a novel partial pattern classification system that uses local binary patterns as a classifier and a content-addressable memory, which has the parallel search capability, to perform classification at a higher speed. The proposed pattern classification system uses Manhattan distance for class assignment and further uses logical resources on the Xilinx Virtex-7 field-programmable gate array to perform classification. Our proposed system assigns a class to a pattern of any size and shape in as less as $1.12~\mu \text{s}$ , which is 33% faster than the state-of-the-art pattern classification system.

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

FPGA Implementation of Weighted Online Sequential Extreme Learning Machine for Data Classification

To design an efficient embedded module field-programmable gate array (FPGA) plays significant role. FPGA, a high speed reconfigurable hardware platform has been used in various field of research to produce the throughput efficiently. A now-a-days artificial neural network (ANN) is the most prevalent classifier for many analytical applications. In this paper, weighted online sequential extreme learning machine (WOS-ELM) classifier is presented and implemented in hardware environment to classify the different real-world bench-mark datasets. The faster learning speed, remarkable classification accuracy, lesser hardware resources, and short-event detection time, aid the hardware implementation of WOS-ELM classifier to design an embedded module. Finally, the developed hardware architecture of the WOS-ELM classifier is implemented on a high speed reconfigurable Xilinx Virtex (ML506) FPGA board to demonstrate the feasibility, effectiveness, and robustness of WOS-ELM classifier to classify the data in real-time environment.

High throughput implementation of SHA3 hash algorithm on field programmable gate array (FPGA)

Cryptographic hash function is an essential element in sensitive communications, such as banking, military and health. It ensures secure communication by checking data integrity, storing passwords and other important roles. Keccak hash function (i.e. SHA3) is the best one in terms of resistance against recent cryptanalysis attacks as well as of hardware performance. However, an efficient improvement in terms of hardware performance is always needed, such as increasing speed or decreasing area consumption. In this paper, we have focused on improving the speed (throughput) of Keccak hash algorithm by proposing a new design which is based on decreasing the number of clock cycles needed to produce a hash value. Consequently, we could achieve 33.35 Gbps as a highest achieved throughput. However, a decrease in terms of maximum frequency has been noticed. Our design has been implemented in Xilinx Virtex5 and Virtex6 FPGA device, and has been compared to recent published implementations.

Beyond the Limits of Typical Strategies: Resources Efficient FPGA-Based TCAM

This letter proposes a novel approach to design a ternary content-addressable memory (TCAM) on a field-programmable gate array (FPGA). The proposed architecture uses slice registers (SRs) for storage instead of lookup tables and static random-access memory, and a control signal in place of a memory element to accommodate a don’t care state. The proposed architecture is implemented on Xilinx Virtex-6 FPGA. Compared with the latest prior work, the proposed TCAM reduces the number of SRs by 50.04% while not compromising on throughput.

SRNoC: An Ultra-Fast Configurable FPGA-Based NoC Simulator Using Switch–Router Architecture

Network-on-chip (NoC) has become one of the most common interconnection architectures to integrate multicore system. However, the performance, hardware costs, and power consumption of NoC are sensitive to many parameters, such as topology, the number and depth of virtual channels (VCs), routing algorithms, and flow control mechanisms. In order to find the best NoC solution for different applications, a fast and flexible NoC simulator is necessary. In this article, we present an ultrafast field programmable gate array (FPGA)-based NoC simulator called SRNoC, which is able to be configured via host on PC. In SRNoC, we proposed switch–router architecture and virtual boundary technology. Switch–router is an architecture which makes SRNoC support irregular or custom NoC topology by configuring the NoC topology in hardware. Virtual boundary is a novel configurable virtualization mechanism which can store boundary traffic and use the stored boundary traffic to simulate large NoC in virtualized mode. By employing the switch–router architecture and virtual boundary, SRNoC demonstrates <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$45\times -3077\times $ </tex-math></inline-formula> speed-up against Booksim and maintains the same level of simulation accuracy. This simulator has three main advantages: 1) configured switch–router can support irregular and custom topologies in a nonvirtualized mode; 2) virtual boundary can improve the simulation speed in virtualized mode, effectively; and 3) embedded models can provide evaluation of packet latency, power consumption, and temperature distribution. Due to the switch–router architecture and virtual boundary, SRNoC can simulate a 30-node ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times 6$ </tex-math></inline-formula> ) NoC in nonvirtualized mode and 3072-node ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times 48$ </tex-math></inline-formula> ) in virtualized mode on a Xilinx Virtex-7 FPGA.

Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.

Efficient Design and Implementation of Energy Detection-Based Spectrum Sensing

Cognitive radio allows opportunistic spectrum access by finding and using temporally and spatially unused radio channels to enhance the utilization of scarce radio spectrum. Various spectrum sensing techniques have been proposed to detect the availability of unoccupied radio channels. In this article, we first briefly discuss the merits of various spectrum sensing techniques. We then present an efficient hardware architecture for energy detection-based spectrum sensing. We discuss various design parameters and features, such as transform length, window selection, window overlap, ensemble averaging, and dynamic thresholding for efficient realization of the designed spectrum sensing module. Then, an efficient hardware architecture for an optimal energy detection-based spectral estimator is presented. To reduce the computational complexity, we utilize a polyphase filter structure. For the high-performance implementation of the proposed spectrum sensing architecture, we use cutset retiming, and for the compact realization, we use the time-multiplexing technique to reuse hardware resources. We model our spectrum sensing module in both floating-point and fixed-point representations using our custom-developed library of numerical operations. The synthesizable parameteric model of the energy detection-based spectrum sensing module is developed in Verilog hardware description language. The architecture of the designed spectrum sensing module is implemented on a Xilinx Virtex-7 field-programmable gate array and operates at 327 MHz. The cycle-accurate bit-true hardware simulation results are verified against its fixed-point software simulation results. An ASIC architecture of the designed spectrum sensing module is estimated to occupy \(5.65\,\hbox {mm}^2\) and dissipate 9.10 mW from a 1.05-V supply while operating at 200 MHz in a standard 32-nm CMOS technology for a 200 MHz bandwidth.

FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Hardware implementation of the proposed direction of arrival (DOA) estimation algorithms based on Cholesky and LDL decomposition is presented in this paper. The proposed algorithms are implemented for execution on a field programmable gate array (FPGA) as well as a PC (running LabVIEW) for the multiple non-coherent sources located in the far-field region of a uniform linear array (ULA). Prototype testbeds built using the national instruments (NI) universal software radio peripheral (USRP) software defined radio (SDR) platform and Xilinx Virtex-5 FPGA are originally constructed for the experimental validation of the proposed algorithms. The results from LabVIEW simulations and real-time hardware experiments demonstrate the effectiveness of the proposed algorithms. Specifically, the implementation of the proposed algorithms on a Xilinx Virtex-5 FPGA using the LabVIEW software clarifies their efficiency in terms of computation time and resource utilization, which make them suitable for the real-time practical applications. Moreover, the performance comparison with the QR decomposition-based DOA algorithms as well as similar FPGA-based implementations reported in the literature is conducted in terms of the estimation accuracy, computation speed, and FPGA resources consumed.

D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs

Ternary content-addressable memory (TCAM) is a high-speed searching device that searches the entire memory in parallel in deterministic time, unlike random-access memory (RAM), which searches sequentially. A network router classifies and forwards a data packet with the aid of a TCAM that stores the routing data in a table. Field-programmable gate arrays (FPGAs), due to its hardware-like performance and software-like reconfigurability, are widely used in networking systems where TCAM is an essential component. TCAM is not included in modern FPGAs, which leads to the emulation of TCAM using available resources on FPGA. Several emulated TCAM designs are presented but they lack the efficient utilization of FPGA's hardware resources. In this paper, we present a novel TCAM architecture, the distributed RAM based TCAM (D-TCAM), using D-CAM as a building block. One D-CAM block implements a 48-bytes TCAM using 64 lookup tables (LUTs), that is cascaded horizontally and vertically to increase the width and depth of TCAM, respectively. A sample size of 512 x 144 is implemented on Xilinx Virtex-6 FPGA, which reduced the hardware utilization by 60% compared to the state-of-the-art FPGA-based TCAMs. Similarly, by exploiting the LUT-flip-flip (LUT-FF) pair nature of Xilinx FPGAs, the proposed TCAM architecture improves throughput by 58.8% without any additional hardware cost.

Efficient Hardware Implementation of Modular Arithmetic and Group Operation Over Prime Field

The need for secure communication over the network has increased drastically over recent years, and Elliptic Curve Cryptography (ECC) carries out a significant role in moving secured information. In this work, a hardware implementation of modular arithmetic and group operations over the prime field for an Elliptic Curve Cryptography Processor (ECP) for an efficient security system is proposed. The modular addition or subtraction operation takes only one clock cycle and the modular multiplication, which is designed using the interleaved modular multiplication method, requires 257 clock cycles. For elliptic curve group operation separate point doubling (PD) and point addition (PA) architectures are implemented in Jacobean coordinates. These new architectures are simulated in a Xilinx ISE 14.7. After that, the architectures are implemented in Xilinx Virtex-7 field-programmable gate array (FPGA) with the VHDL language. Proposed modular arithmetic and group operations can be utilized to design an Elliptic Curve Point Multiplication (ECPM).

A FPGA-based state space controller

For many years digital controllers have been implemented using microprocessors, microcontrollers, digital signal processors etc. Recently, field programmable gate arrays (FPGA) is found to be an alternative because of its high processing speed. In this context, this paper presents the implementation of state space controller (SSC) on FPGA. SSC contains an observer to estimate the system unknown states variables. Matrix multiplications involved in this estimation take most of the computation time of the controller. In order to make SSC much more competent for controlling fast dynamic systems, a new FPGA based parallel architecture is proposed. The reduction in computation time with optimal hardware resources is achieved by developing an efficient multistage matrix multiplication algorithm (MMM). The performance of FPGA-based SSC is validated by implementing it in an inverted pendulum control system. The design is mapped on xilinx virtex-5 FPGA device with a maximum frequency of 449.438MHz.