FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Ahmed A Hussain,Redha M Radaydeh,Abdel-Hamid Soliman,Nizar Tayem

doi:10.1109/access.2019.2926335

Ahmed A Hussain, Redha M Radaydeh + Show 2 more

Open Access

https://doi.org/10.1109/access.2019.2926335

Copy DOI

Journal: IEEE access : practical innovations, open solutions	Publication Date: Jan 1, 2019
Citations: 21	License type: CC BY 4.0

Abstract

Hardware implementation of the proposed direction of arrival (DOA) estimation algorithms based on Cholesky and LDL decomposition is presented in this paper. The proposed algorithms are implemented for execution on a field programmable gate array (FPGA) as well as a PC (running LabVIEW) for the multiple non-coherent sources located in the far-field region of a uniform linear array (ULA). Prototype testbeds built using the national instruments (NI) universal software radio peripheral (USRP) software defined radio (SDR) platform and Xilinx Virtex-5 FPGA are originally constructed for the experimental validation of the proposed algorithms. The results from LabVIEW simulations and real-time hardware experiments demonstrate the effectiveness of the proposed algorithms. Specifically, the implementation of the proposed algorithms on a Xilinx Virtex-5 FPGA using the LabVIEW software clarifies their efficiency in terms of computation time and resource utilization, which make them suitable for the real-time practical applications. Moreover, the performance comparison with the QR decomposition-based DOA algorithms as well as similar FPGA-based implementations reported in the literature is conducted in terms of the estimation accuracy, computation speed, and FPGA resources consumed.

Highlights

Source localization or direction of arrival (DOA) estimation of a radio frequency (RF) signal is a very important component in many practical applications such as channel estimation, beamforming, radar and sonar tracking, multiple-input multiple-output (MIMO) systems, etc
We propose two DOA estimation techniques based on LDL and Cholesky factorization for hardware implementation
The work presented in this paper establishes the superior performance of proposed LDL and Cholesky-based DOA estimation algorithms for field programmable gate array (FPGA) hardware implementation over existing methods reported in the literature

Summary

INTRODUCTION

Source localization or direction of arrival (DOA) estimation of a radio frequency (RF) signal is a very important component in many practical applications such as channel estimation, beamforming, radar and sonar tracking, multiple-input multiple-output (MIMO) systems, etc. Performance of the proposed algorithms has been measured in terms of estimation accuracy, count of FPGA resources consumed, and computation time, and has been compared with QR1 decomposition-based DOA estimation methods (QR-Q, QR-R). Propose two computationally efficient DOA estimation algorithms based on Cholesky and LDL decomposition suitable for FPGA hardware implementation For these algorithms, only the lower triangular matrix needs to be computed for extracting angle information estimates. One distinct advantage of the proposed methods is that it is sufficient to compute only the lower triangular matrix L for determining the DOA estimates of incident RF sources This reduces processing time as well as memory storage requirements. The DOA information is extracted from the signal space contained in the lower triangular matrix L, and the least squares (LS) approach is used to obtain the direction matrix

PIPELINED ARCHITECTURE IMPLEMENTATION

IMPLEMENTATION OF PROPOSED ALGORITHMS ON FPGA

PERFORMANCE COMPARISON

Findings

CONCLUSIONS