High Speed Partial Pattern Classification System Using a CAM-Based LBP Histogram on FPGA

Abstract

This letter proposes a novel partial pattern classification system that uses local binary patterns as a classifier and a content-addressable memory, which has the parallel search capability, to perform classification at a higher speed. The proposed pattern classification system uses Manhattan distance for class assignment and further uses logical resources on the Xilinx Virtex-7 field-programmable gate array to perform classification. Our proposed system assigns a class to a pattern of any size and shape in as less as $1.12~\mu \text{s}$ , which is 33% faster than the state-of-the-art pattern classification system.